how to design a Low jitter Clock for Data Converter?

[xdunicorn]

My data converter is AD9863. My ADC sample clock is souced from FPGA.
The sample clock from FPGA isn't clean. The ADC sample clock frequecy is 15Mhz.I find that noises are introduced into my system. I have some problems about Clock. The sample clock can be sourced from FPGA?If not,how can I do? Thanks a lot.

 

[eda4you]

My data converter is AD9863. My ADC sample clock is souced from FPGA.
The sample clock from FPGA isn't clean. The ADC sample clock frequecy is 15Mhz.I find that noises are introduced into my system. I have some problems about Clock. The sample clock can be sourced from FPGA?If not,how can I do? Thanks a lot.

first place the oscillator as close to the converter as you can in order to avoid emc coupling as also getting more jitter on the clk input pins. jitter in the fpga don't worry therefore the fpga can be more far away of the crystal oszi, but even not to far --> otherwise you will even get more problems. Seperate the ground and supply into seperate ones. Connect the AGND and DGND at a system star ground very close to the power supply.

I don't know what's your Fs, but as I can remember this adc is able to have 12bit@80MSPS--> Therefore you must have a jitter of the crystal oscillator as low as 1ps--> which is defenitely very low!! Take a GOOD crystal oscillator as such von Wenzel Associates having a rms jitter below 0.5ps.

Hope i could help.

 

[chinara]

Another important factor you should take care is the power. The noise overlaps the power will add jitter. So add capacitor between the power and ground pin, and make the power plane and ground plane as near as possibl. It will helpful to supress the noise by adding prectect ground beside the clock trace.
Maybe you also should find the source of noise, or it is difficult to supress the noise completely.

 

[elcielo]

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