Problem with FIR filter taps

[xdunicorn]

Fir filter tap

Hello everyone:

I need some help about my problem :

Now I use a FIR filter IP core of xilinx. This filter is used for a 12 bit DAC.
The filter is low pass filter .It's taps is 39 and input data width is 12. I want to put a 12 bit dac directly connected to the output bus of fir filter. But I find FIR filter's output data width is much greater than 12 . The filter's output data cann't be used directly by a 12 bit dac . How can I solve this problem?

Thank you very much!

 

[andy1]

Re: Fir filter tap

Since the DAC is a 12 bit resolution dac, I don't think it can handle more than 12bit width, unless the DAC architecture allows for more than 12bit resolution by taking in two 12bit successively but I doubt it.

If that is the case than you might have to find a FIR filter that will output data with 12bit resolution at a time. If you must absolutely need more than 12bit resolution then you might have to use a different DAC.

Or you can chop off some lsb bits for the FIR so that the data can fit into the DAC if you can live with the reduced resolution.

 

[fxiao]

Re: Fir filter tap

What you need is scale stage after FIR and before DAC.

 

[zorro]

Fir filter tap

Hi xdunicorn,

you can use the 12 most significant bits of the result. In order to cancel the small bias (dc term) due to truncation, you should round the result adding 1 to the 13th bit before truncation.
In order to consider a possible optimization, please give this information:
How many bits has the output of the filter?
How many bits have the coefficients of the filter?
Regards

Z