Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
low pass filter 3 hz
2. Transconductance Amplifier Strucutres with very small transconductances: A comparative design approach, IEEE Journal of Solid-State, Vol 37 No.6 June 2002
measuring port capacitance
Let say I have a combinational logic gates which have 1 input node and 1 output node.
In Cadence, what method to use to measure the input capacitance (Cin) and output capacitance (Cout) of these two nodes?
Normally when we disable/off/sleep/standby an IC, I noticed all outputs are usually set to high impedance state (tri-state) instead of HIGH or LOW.
What is the reasons behind this?
Re: PLL: Cycle slipping detector, lock detection, please hel
Reply from safwatonline,
Hello wylee,
i dont have too much information about the lock detector except the basic operation, but here is what i think anyway:
the cycle slipping seems to be good and simple way to detect the lock but it...
cycle slipping pll
Referring to the circuit posted by safwatonline,
For lock detection,
what are the problems/disadvantages of using a cycle slip detector (cycle slipping detector) connected as below?
1. Will there be any false detection? (e.g: when same clocks phase but different...
Re: Measure S-Parameters for TIA in Cadence
1. It seems that when you use PORT, you need to fill in voltage amplitude information in PORT's properties (psin). But circuit input (IN) is current driven, it this still applicatable? or do I need to add a 1Ω resistor in series with the port to...
how to measure s-parameters cadence
I wish to know how to measure S-Parameters S21 of this circuit in Cadence
What kind of setup and measure procedure I need? I want to plot dB20 vs Frequency
convert from 1.8v to 3.3
Can you attached a small diagram describing the connection for proper understading? And I am using this in chip level IC design...so I won't be getting discrete component like 2N7002
ic which convert 3.3v dc to 1.8v dc
DenisMark,
This is the book you are referring right?
Basic ESD and I/O Design
by Sanjay Dabral, Timothy Maloney
Hardcover: 328 pages ; Dimensions (in inches): 0.88 x 9.52 x 6.41
Publisher: Wiley-Interscience; 1 edition (November 30, 1998)
how to convert 1.8v to 3.3v
IanP,
Actually, I was hoping to know the internal circuit/schematics of such translator instead of buying/using the chip you recommended.
how to convert 5 logic to 3.3
I would like to
1. convert a digital logic signal from 3.3V to 1.8V
2. convert a digital logic sginal from 1.8V to 3.3V
What kind of circuit which can achieve this without degrading the signal quality (e.g: duty cycle) ?
ahdllib
I want to use a square wave vco to run some test on my circuit, I found this "dig_vco" cell inside "ahdlLib" but I can't make it work
Can anyone teach me how to configure this component?
I am ramping a voltage source from 0.7V to 1.4V (within 0s to 1u)
Attached is the snapshot of...
Questions in PLL
I recently read up about "Dead Zone" faced in PFD.
Is "Dead Zone" the only big problem in designing a PFD?
Here is a report done by student (i think) i foung on web,
which use a delay chain to minimizie dead zone in classical PFD (2 DFF, 1 AND type PFD)
**broken link...
Newbie questions in PLL
Its seems that using charge pump PLL architecture is quite common practice nowdays.
Instead of using active/passive loop filter, charge pump with a cap replace that block. What is the advantage & disadvantage of using a charge pump in PLL?
In the case of PFD, the PFD...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
