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Recent content by wsy979

  1. W

    What's the best architecture for a high speed ADC?

    high speed ADC Dear Yaqi what I said is different with the paper of Bright, he used one s/h for each slice, but I was thinking about only one s/h for the adc driving all the slice.
  2. W

    Help me correct second harmonic jump in front end SHA of 12bit pipelined ADC

    SHA fft (SNR SNDR) dear ljy4468 you said "second harmonic jump", bu so far as i know, 12bit adc need full differential structure. and third harmonic is the most lager distortion did you use the single ended structure?
  3. W

    question about the requirement of opamp used in the ADC

    to dear sunking could u plz explain how the the -3db bandwidth generate the gain error or plz tell me what should i refer to for finding out the explanation thx regards
  4. W

    question about the requirement of opamp used in the ADC

    i think it is not a must i have done an OTA for S/H,it seems that the -3db bandwidth doesnot affect the error
  5. W

    What are the causes of residue drop in ADC?

    Residue drop in ADC dear moisiad i think u'd better check the gain and settling time of residue-amp but why not use 1.5 bit per stage regards
  6. W

    problem with gain error in S/H amp .

    dear manish i am not very clear about your S/H schemetic, and your CMFB circuit. Much things in S/H affects the gain error, including the specifies of OTA, the sample switch and sample cap. For the close loop OTA, its gain, UGB, input and output common mode voltage and the feedback factor...
  7. W

    Errors when extracting DAC layout

    Re: HELP REGARDING DAC try to refer book on principle of data converters such as Razavi's "principles of data converter system design" , chapter 4 hope it helps regards
  8. W

    Conversion rate ADC ?

    conversion rate adc wiki Ms/s=Mhz Samples per Second but im not sure about Mb/s
  9. W

    10-bit pipeline ADC at 6.75Mhz for imaging application ?

    would u post an architecture diagram let us kn more about ur pipelined ADC
  10. W

    HOW CAN I MODEL THE OPAMP THE MATLAB

    operation amplifier matlab thx for ur sharing but I find that the ppt file in the zip is cracked, it has crc check error would you plz post check it ? regards
  11. W

    Design flow of mixed signal design in relation to CMOS technology

    mixed signal ADC/DAC must be very good examples a good doctor dissertation can help you a lot regards
  12. W

    What's the best architecture for a high speed ADC?

    high speed ADC to yagi for case 2 Doudle sampling tech usually applied in filters,ΔΣ modulators and pipelined ADCs without speed up the OTA. But OTA'srecovering time may affect doubling the sampling speed. While double sampling need more switches, which can produce more distortion in T/H...
  13. W

    What's the best architecture for a high speed ADC?

    high speed ADC expecting I am thinking of the same question like yaqi regards
  14. W

    can Switch Capacitor CMFB, redue the over all gain of a OTA

    Re: can Switch Capacitor CMFB, redue the over all gain of a well, I have met same question s/c cmfb need time to settle. while ac analysis perform at 0s, before cmfb settled. I think you can make an ideal cmfb to replace s/c cmfb for ac analysis. Btw: s/c cmfb can reduce the gain bandwidth...
  15. W

    SNR issues in pipeline ADC

    SNR in pipeline ADC 1st 1pf sample capacitor for a 10bit ADC is too small. Acording to limit of kt/C noise, the capacitor should be larger than 1.5pf, and this affect SNR a lot. 2nd I don't know whether you use close-loop OTA or open-loop one, that is important for ENOB of ADCs.
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