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Recent content by woodyplum

  1. W

    standard cell library design

    internal power of a standard cell SNPS have tools can do it for you from the spice level, check it in SOLD
  2. W

    How to creat a random data in verilog!

    $random, the verilog LRM or IEEE standard should be the best reference
  3. W

    EPROM , EEPROM , SRAM , DRAM

    search in any basic circuit book, you can find the answer. EPRON are using the electron in gate oxiside. sram are using transistor structure(commanly 6) while dram using Cap.
  4. W

    The difference between low speed and high speed buffers

    different Buffers they should have different transitor size there fore different drive strength, you can see it in the cdl part(spice for LVS) in your library.
  5. W

    What are the efficient coding styles in Verilog/VHDL?

    Coding style may be you can check some LEDA rule or nlint rule, will helpful
  6. W

    Verilog RTL and Behavioral Testbench

    two total different descrition, only the same if you are waiting for the occur(one time event) of the En, in this status the later one should be more efficient
  7. W

    how assign statement can be implemented?

    in behav level, i don't think assign have any problem. the problem only occur when you implement in PR tools
  8. W

    Mix Analog and Digital design verification??

    many tools can fit your work, VCS+NS shoule be popular, you can run your dg with vcs and analog with nanosim, or config both at spice level
  9. W

    questions about hspice installed on Linux7.3

    thanks, ihave the same problem
  10. W

    Can I have a triple boot PC with Fedora core 3, Windows XP and SuSe

    Re: triple boot Firstly, the Linux Installer may do this for you. If it doesn't set tripple boot automatically, at least it can set double boot for you. After installing the second linux, you can merge the two /boot/grub/menu.lst file -- one from the first linux and the other from the second...
  11. W

    Hspice and Cadence Spectra

    sepcctra cadence how about the RF feature for these two?
  12. W

    RHE 3.0 for using EDA on notebooks

    To use EDA on Notebook mine is asus m50, can i use it?
  13. W

    Is there any tools can help FSM analysis and design

    stateCAD in ISE package and other tools likw activehdl and help you

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