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Generally except VDD/VSS power pads, most input/ouptut/inout pads can be used for boundary scan. First let function logic designers select pads that meet their function needs then DFT engineers build the boundary scan chain and tap logic.
That depends on the ATPG tool you're using. Please read the verilog testbench generated. There should be some signals representing pattern count. If you're using Mentor's tessent, have a look at "_pattern_count".
A good question. There are a lot of trade off here. My two cents. One is that RAM is not easily portable while registers in RTL are easily portable to other processes. If you give your RTL as IP to mutiple customers or you design for multiple processes, portability would be a factor. The other...
I think you're talking about DRCs in tessent tool. AFAIK, Scan DRC is for pre-scan drc and ATPG DRC is for post-scan and pre-ATPG. Yes, there are some DRC for checking EDT when you switching to analysis system mode.
Generally pad cell libraries are separated from normal standard cell libraries. Those libraries' names are much different from those standard cell ones.
For formality, most optimization including retiming are stored in svf file that you need not much extra user input. For Conformal, there are some commands like 'analyze retiming' for retimed modules.
IIRC, edt parallel patterns do not simulate edt logic.They only force 0/1 on flops' SI pins. So if serial patterns fail, there might be something wrong on scan paths.
What are the not-mappped DLATs are? Are they clock gating? Have you turn on clock gating remodelling? It is abnormal because there are often not much clock gating in RTL.
Those runs have same tool settings? Usually there might be some very small difference(not exactly the same, but in a close range) if design inputs are same and tool settings are same. It's due to heuristic algorithms used in tools that might not generate same results in different runs.
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