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Recent content by win2010

  1. W

    eliminating intermediate delay

    Yes, randomizer will start with 5 bit header and later 20 bits data.... I am trying to increase the buffer read rate than write, so i can manege these extra bits throughout my program. - - - Updated - - - My next difficulty is reading data at 5/4 * clk_frequency. I can do double clock rate...
  2. W

    eliminating intermediate delay

    Thank you....... But my next block is randomizer(PRBS). Which will start with a Header(5 - bits) first and later 20 bits data. I maintain one extra buffer for 20 bit data also which is overflowing because next header will come when I outputting 20 to 25th datas of previous.
  3. W

    eliminating intermediate delay

    Yes first time i did`t get so only i further post new one. Thanks "ads-ee". Your post clearly says all possibilities. to "ads-ee" : please little bit elaborate your (c) answer. How to do two different clock for read and write...? (read is faster than write)
  4. W

    rate mismatch between input data to output data

    by taking 32128 bits of data i need to send 32208 bits of data... Means, my logic generates extra 80 bits for input and send to next module... 32208 = 32128 + 80 bits of header
  5. W

    rate mismatch between input data to output data

    Hello, I need to send 32208 bits of serial data within the 32128 clock per bit of input in VHDL..... How to do this rate change between input and output...? output has more data than input....
  6. W

    eliminating intermediate delay

    My question is simple, I need to send 32208 bits of serial data within the 32128 clock per bit of input..... How to do this rate change between input and output...? output has more data than input....
  7. W

    eliminating intermediate delay

    Hello, Input bits are continuous but I need add Header for each and every time, so only I`m missing input. I designed this by taking Buffer but this is going Overflow after some time. Ex: I had continuous input bits and for each and every 20 bits of input I need to generate 5 bits of Header to...
  8. W

    solution for large memory requirement for FPGA

    Hello, I am designing "time interleaver" for DVB-T2, which is require large memory to be store before interleave. Means, 32400 values in a one row and like that 1024 column of data need to be store before doing operation. 32400 rows, 1024 columns and each location of 17-bits wide. 32400...
  9. W

    How to increases Maximum operating freqency

    library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity map1 is port(clk:in std_logic; reset:in std_logic; code_rate:in std_logic_vector(3 downto 0); mod_mode_sel:in std_logic_vector(1 downto 0); N_ldpc:in std_logic_vector(15 downto 0); input1:in std_logic...
  10. W

    Error in Post-synthesis, ModelSim

    I given like that both are also not working: process(clk, reset) Process(count2) what to do for this, to come out of this loop...?
  11. W

    Error in Post-synthesis, ModelSim

    This is code for finding CRC for all combination of inputs. I cheked this before synthesis which is working fine but after synthesis giving error as bellow. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all...
  12. W

    how to implement interleaver in FPGA

    My interest is to use behavioral description only...But not getting source(idea or usage for large value) to design..if i understand little bit then can able to write.... where i can get this...?
  13. W

    how to implement interleaver in FPGA

    Yes, thank you.... i worked on USB 3.0 physical layer design and UART.. But this is entirely different design what i doing now... If you have any materials for complex design pls give me... like design guide,,,, I go through many PDFs no were i found what i wanted....
  14. W

    how to implement interleaver in FPGA

    Yes,your right.....I designed many blocks but never i got problem like this. So i continue with same procedure i stuck here.... I studied VHDL before start but no were i find do`t use too large signal or variable..... Suggest me what is next thing to do..........
  15. W

    how to implement interleaver in FPGA

    Hi.......... I attached image of DVB-T2 "Bit-Interleaver" in that columns and Rows are given. This is for 16-bit QAM and length is 64800-bits. This divided into 8100 rows and 8 columns. The data coming from previous block is "one Bit per Cycle". First bit store in 0th location like that First...

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