how to implement interleaver in FPGA

[win2010]

Hi..........

I attached image of DVB-T2 "Bit-Interleaver" in that columns and Rows are given. This is for 16-bit QAM and length is 64800-bits. This divided into 8100 rows and 8 columns. The data coming from previous block is "one Bit per Cycle". First bit store in 0th location like that First 8100 bits should store and later shift these bits circularly(ROTATE) according a "twisting parameter tc" listed in table below. Next 8100 also twist and store...so on up to 8 columns...

Write into Buffer(storage) as ROW wise:-
input indexs: 0 1 2 3 4 5 6 .... 8099
after circular 0 1 2 3 4 5 6 .... 8099
shitf using "tc=0"


if "tc=2" then 0 1 2 3 4 5 6 .... 8099
.................8099 8098 0 1 2 3 4 5 ...8097

this is upto 64800 bits and Reading(output) these twisted bits as column wise..like 0th location bit first,8099th second,serillaty 16199,24298,32397,40496,48595,56694,64793, 1, 8100, 16200...so on.....

I design using signal and variables in VHDL which is not synthesizing....
help me what best way of implimentation....

 

[TrickyDicky]

I really think you need to start over. Go and work through a VHDL tutorial, preferably one that is designed for synthesis. You need to understand the basic elements you are trying to implement before you can even think about something complicated like this.
Your comment "I design using signal and variables in VHDL which is not synthesizing...." makes me believe you dont understand the basics well enough.

 

[win2010]

Yes,your right.....I designed many blocks but never i got problem like this. So i continue with same procedure i stuck here....
I studied VHDL before start but no were i find do`t use too large signal or variable.....
Suggest me what is next thing to do..........

 

[TrickyDicky]

Think about how the design needs to map to hardware. Draw the circuit out without writing any code. Cant do that? then you need to do more learning. Start with smaller projects. This project is going to be rather complicated, and require a lot of look up tables.

 

[win2010]

Yes, thank you.... i worked on USB 3.0 physical layer design and UART.. But this is entirely different design what i doing now...
If you have any materials for complex design pls give me... like design guide,,,, I go through many PDFs no were i found what i wanted....

 

[FvM]

i worked on USB 3.0 physical layer design and UART.. But this is entirely different design what i doing now...

Don't think so, it's still basic hardware logic design.

I presume it will use block RAM for efficient resource utilization, so the essential point is to fulfill the requirements for RAM synthesis. If you have difficulties to write a synthesizable behavioral description, it might be easier to use a structural description starting with a RAM component from the vendor library (respectively the core generator or "MegaFunction" provided in your FPGA tool. Design the data path and control signals around the RAM block to connect it to the interleaver input and output data.

A simple starting point could be a 1-bit wide dual port RAM with respective address generation on both sides.

 

[win2010]

My interest is to use behavioral description only...But not getting source(idea or usage for large value) to design..if i understand little bit then can able to write.... where i can get this...?

 

[TrickyDicky]

Behavioural code is no use unless you understand the underlying hardware. Without understanding, at best it will use logic innefficiently or at worst, just not work at all.

Behavioural description can be used very effectively when you follow the coding guidlines from your chosen chip manufacturer.