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Re: PMOS switching leakage current flow and power.
Hi Rajkumar, thanks for the reply.
The input voltage is 0V to 1V only. PMOS will turn on when input voltage is 0V.
Since current is negative, P=VI, how is the power is positive? Please enlighten me.
Thanks.
If you use tanner, add .op to find operating point. It will give you static power.
For dynamic power, take inverter for example, perform a DC simulation at input. The power is peak when Vin=Vout. Measure the power from 0 to 1V. Dynamic power = Total power - static power.
For an inverter, PMOS is at top and NMOS bottom. Vdd provide voltage to PMOS.
Lets say node A is node where Vdd and PMOS source join,
when DC analysis is performed at the gate input,
the leakage current will peak at Vin=Vout.
Node A will be a negative current, since PMOS current is negative...
I got the above waveform. I need to get like below:
It's switching leakage current. How do I do? Below is my code.
__________________________________________________________
Vdd vdd gnd dc=1v
* --- Source ---
Vgate gate gnd 0
* --- 1 unit Inverter ---
Mp1 drain gate vdd vdd pmos1 W=20um...
SRAM butterfly curve - HSPICE / CosmosScope
Greetings. I wish to ask for method to create butterfly curve. It's V(q) vs V(qb). When I use DC analysis, I can sweep voltage q and observe voltage at qb, but the voltage q will be a linear increase straight line. If I were to observe the transition...
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