PMOS switching leakage current flow and power

[warlocklw]

For an inverter, PMOS is at top and NMOS bottom. Vdd provide voltage to PMOS.

Lets say node A is node where Vdd and PMOS source join,
when DC analysis is performed at the gate input,
the leakage current will peak at Vin=Vout.

Node A will be a negative current, since PMOS current is negative when turned on.
So, since P=VI, the DC analysis is positive voltage of 0 to 1V,
will the power also negative?

How is possible that power is negative, since it means we gain more power by turning on the device.

Any idea? Thanks.

 

[rajkumar@carc]

Re: PMOS switching leakage current flow and power.

For an inverter, PMOS is at top and NMOS bottom. Vdd provide voltage to PMOS.

Lets say node A is node where Vdd and PMOS source join,
when DC analysis is performed at the gate input,
the leakage current will peak at Vin=Vout.

Node A will be a negative current, since PMOS current is negative when turned on.
So, since P=VI, the DC analysis is positive voltage of 0 to 1V,
will the power also negative?

How is possible that power is negative, since it means we gain more power by turning on the device.

Any idea? Thanks.

Rajkumar:::
PMOS WILL ON ONLY WHEN INPUT VOLTAGE IS NEGATIVE.
AND CURRENT YOU GET IS NEGATIVE.
THERFORE POWER IS POSITIVE.

 

[warlocklw]

Re: PMOS switching leakage current flow and power.

Hi Rajkumar, thanks for the reply.

The input voltage is 0V to 1V only. PMOS will turn on when input voltage is 0V.
Since current is negative, P=VI, how is the power is positive? Please enlighten me.

Thanks.

 

[dick_freebird]

All this negative / positive stuff is just convention that
you're confusing yourself over. If you get the current-
flow-direction convention straight then (DC) power will
always be positive (dissipated).

It looks to me more like some of your assertions /
assumptions to this effect are untrue, than that there's
some surprising violation of physics that you're the first
to notice.