Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Some references say: An ultra low-distortion filter is used to generate a spectrally pure sine wave before the ADC.
My question is why the linear requirement is so urgent? How about a medium low-distortion and good stop-band attenuation BPF? It also can remove high HD and get a pure single...
I used PSS to simulate the opamp's 1dB compression point in SPECTRL, I found that the output signal swing is higher than vdd at the gain decreased by 1 dB comparing with small signal gain. The result puzzled me. The output voltage is distorted in large signal input. And the input signal must be...
Hi, Jeff
From some reference, it is recommended that the dampling factor is set to 1. And I think i cannotget the jitter peaking from simulation. I can only get the pnoise.
I used ring oscillator
thanks
Hi Jeff,
I understand your point. From Thomas Lee's paper on JSSC 2000, PM is only a function of c1/c2 and the crossover frequency ωc=((b+1)**½)/τ. According to his formula, i calculate the parameters with my design value, PM is 56.4•,ωc=1.3M.I think PM maybe is not a issue.
Thanks for your...
Hi Jeff,
I understand your point. From Thomas Lee's paper on JSSC 2000, PM is only a function of c1/c2 and the crossover frequency ωc=((b+1)**½)/τ. According to his formula, i calculate the parameters with my design value, PM is 56.4•,ωc=1.3M.I think PM maybe is not a issue.
Thanks for your...
hi,jeff
the damping factor is 1, from the trans simulation, settle is good.
zero is 0.4M,the third pole is 4.2M,loop bandwidth is 1.5M.Do you think it is suitable?
thanks
Dear rfsystem, thanks for your reply.
As you said, the pll bandwidth is lower and I should make it a little bigger, is it right? I should
fine tune the loop filter parameters R C1 and C2 (third order system)? Would you like to give me
some suggestion? Thank you very much.
Dear suederb, I...
Thanks for your help in advance.
My reference clock is 20MHz,charge pump current is 50uA, Kvco is 380MHz/V,divider N is 12. I select loop bandwidth of 1.5Mhz, and the simulated trans and pnoise is as below. From the trans, the system is stable. But in the pnosie figure, I don't know why the...
Thank simon110 very much for your help. I have other questions.
/1. you said your sampling rate is 40MSps, so the input signal fre. should below 20MHz, so if your input fre. is 51MHz, the spectrum will overlapp each other, the sharp drop of SINAD is inevitable./
You are right, the spectrum...
Thanks, ezt and simon110
I did trans simulation with different input frequency,and took fft with matlab. I got the SINAD of 79.8dB at Nyquist rate (sampling rate is 40MSps), that correpond to 13ENOB. When i increased the input frequency to 51MHz, I found that the SINAD droped to 67dB(11ENOB). I...
We can see the layout of pcell----rfnmos and rfpmos from TSMC, it only extended DIFF IMP area and added two more poly rails around mos device, without connecting dummy poly with other wires.
Hello, everybody. I have a question for help: When i design a sample/hold circuit, I want to know how to evaluate the performance.
SHA is a critical component. I think I should do trans simulation and take fft. Is it ok? In general, for 10bit adc, what is the spec that SHA should achieve...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
