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Recent content by Vonn

  1. V

    simulation completed, what next...?

    It might be also a good idea to consider ChipScope (to insert logic analyzer, bus analyzer, and virtual I/O low-profile software cores directly into your design) for testing and debugging purposes. -Vonn
  2. V

    [Synopsys vcs] Segmentation fault when running ./simv

    Hello, I am trying to use Synopsys vcs to compile and simulate a simple vhdl design. vhdlan and vcs worked fine but I am now getting a "Segmentation fault" error message when I run %./simv to simulate my design I noticed that the tool gives me the following warning at the beginning...
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    What is the power analysis?

    Re: Power Analysis I have a question regarding power analysis. I developed a new design (VHDL-based) and want to do power analysis (dynamic and static) for various technologies such as 0.18u and 65nm technology. My question is : Is there any power analysis tool that can do this job. I mean...
  4. V

    hardware circuit design

    Thanks guys: artem: You have a good solution but there is one problem : how can you make sure that your pushbotton will be on enough time so that uc can be initialize the port ? I will not mention the debouncing because RC can solve it but If I applied your design I will have to use monostable...
  5. V

    hardware circuit design

    I need to design a power circuit for my microcontroller such that: 1- It works (connects controller to vdd) when a push button is clicked 2- microcontroller stays on until it receives an input signal (let's say it's input1) 3- Once controller receives this signal it sends a control signal...
  6. V

    Question about Atmel controller

    ramesh, you are right but to load the LUT do I have to do it manually ini the bin editor after I got the bin file ? Another Q: Is it possible to program this controller on circuit without adding any extra hardware ? shafee001 Thanks but I mean to use the uc internal flash and EEROM mondunno...
  7. V

    Microcontroller Design issue

    issue of microcontroller I need a microcontroller that has the following features 1- I Can put 30K LUT inside its flash ROM 2- I Can save a number and keep it after turning off the controller and then reload it and change it next time it powers up 3- I can program it on circuit using In...
  8. V

    Question about Atmel controller

    1- Is it possible to use nonvolatile memory in AT89C51AC3 while it's running? I mean Can I save a number and keep it after turning off the controller and then reload it and change it next time it powers up and so on? 2- Can i save 30K lookuptable in the 64KB flash while writing my code? is it...
  9. V

    SystemC 2.0.1 configuration error on CentOS

    systemc configure Thanks Nevr0 , I tried what you said but the only architecture option I have found is related to Directory and file names ... here is what I got ../configure --help Usage: configure [options] [host] Options: [defaults in brackets after descriptions] Configuration...
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    SystemC 2.0.1 configuration error on CentOS

    Hi guys , I am new to linux and systemC so forgive me if it's a trivial question but I have a problem when I tried to configure systemC V2.0.1 on CentOS I followed the install-file instructions but when I tried to config. I got the following message: creating cache ./config.cache...
  11. V

    LVS, DRC, and analog simulation ?

    thanx gliss , when I looked at the Cadence Assura manula , the first step says: In the Layout Editor, select Tools, Assura from the menu.... actually Iam using SILICON ENSEMBLE as my P&R and i can't see (tools) in the menu? Do they mean another tool other than SILICON ENSEMBLE as a layout editor?
  12. V

    LVS, DRC, and analog simulation ?

    Hi guys , Iam doing my first ASIC design , Iam using VIRTUOSO SPECTRE CIRCUIT SIMULATOR as my simulator tool from cadence and DESIGN ANALYZER as a synthesis tool from synopsys and SILICON ENSEMBLE PKS as my place&route tool , up to know I did the simulation , synthesis , p&r and every thing is...
  13. V

    use of parameters in verilog

    don't you think using parameter - for FSM - for example will force the synthesis tool to encode your state control to the one you wrote in your parameter definition even if was not the optimum technique for FSM state encoding ?, i mean you just use parameter - usually in FSM - to make your code...
  14. V

    Getting started w/ ASICs - request for resources

    Re: Getting started w/ ASICs you can just search here for asic and you will find many answers but I will recommend to start first with the design flow h**p://vlsi.ee.hacettepe.edu.tr/tutorials/tutorial_yildirim/tutorial.htm
  15. V

    what is the difference between #1 a<=b and a<=#1 b

    sure it does ... here is an example : if you write in your process : a = 1; b = a; c = b; these are Blocking assignment a = b = c = 1 and the generated circuit will be a 3 buffers connected to each others 1 ---[buffer]--->a---[buffer]--->b---[buffer]--->c while if you write it using...
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