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Recent content by VLSI@91

  1. V

    max_transition limit

    Hi, Why is max_transition limit is specified on top of library limit. When the foundry suggests the cell can withstand the lib limit transition why is this extra trans limit given? Thanks
  2. V

    violations of block seen at top

    Hi jbeniston, Could you please explain more on clock timing part of your reply? Thanks
  3. V

    violations of block seen at top

    Hello I have a question . If suppose I have closed my block and there are no reg2reg violations. And the same block has been plugged at top and here during flat analysis i am seeing reg2reg violation whose startpoint and endpoint are at block level. How is this scenario possible when i have...
  4. V

    Scan shift and capture timing

    hi, can you be more clear with your question?
  5. V

    regarding CCS library

    thank you. will try out with DC compiler :)
  6. V

    regarding CCS library

    can anyone tell me how are these transition values calculated? does these values depend on resistance and capacitance values? here is the snap shot of CCS library file(i.e the values present in the index) cell_fall ("xyz") { index_1 ("0.0076758, 0.0154251, 0.0309978...
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