violations of block seen at top

[VLSI@91]

Hello

I have a question . If suppose I have closed my block and there are no reg2reg violations. And the same block has been plugged at top and here during flat analysis i am seeing reg2reg violation whose startpoint and endpoint are at block level. How is this scenario possible when i have closed my block completely? Thanks in advance

 

[jbeniston]

A block isn't isolated from the rest of the die. Wires outside of your block can couple to nets inside it, effecting timing. Perhaps the clock timing isn't quite what you assumed it to be.

 

[VLSI@91]

Hi jbeniston,

Could you please explain more on clock timing part of your reply?

Thanks

 

[sharath666]

The best approach here is to complete the analysis for your block and then declare your block as a don't touch when doing analysis at the top level. This should retain the timing characteristics for your block.

 

[jeevan.life]

As mentioned, during block closure, you have budgeted values for the clock. While instantiated in the top, the clock arrival might be different from that you have specified and hence the violation.

Other thing is if wires are running over your block, they can have crosstalk effects due to coupling and cause violations.

Final possibility is that the clock path itself has coupling with other nets at top and the shifting arrival windows cause coupling in the block.