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Recent content by vizpal

  1. vizpal

    DDRn Split Controller application space

    Where do we make use of a "DDR Split Controller Configuration" ? What is its advantages/dis-advantages ? From what I understand, in Split Controller configuration - 2 controllers share the same cmd/addr PHY but have independent DATA PHY. The PHY frequency is going to be the same as that of the...
  2. vizpal

    setup and hold time (interview question)

    h do u fix hold time violations Good explanations ...
  3. vizpal

    BAD Block config in NAND Verilog Model !!

    micron nand verilog model I have downloaded a NAND Verilog Model from the Micron Site. I want to check if my NAND Controller is performing Block Hunting correctly. For this how can I create some BAD Blocks. I understand that I need to create some value other than 8'hFF in the spare region...
  4. vizpal

    System Verilog rtl question . . . ! ! !

    Can we define this as part of interface file ???? :idea:
  5. vizpal

    System Verilog rtl question . . . ! ! !

    Hi, I am working on a SV verification project. I want to access some internal rtl signals in my Testbench. How is this done ??? I came across "$root" in SV, but am not sure how to use it !!! Can anybody explain me how this can be done... If possible give examples... Thanks in advance ...
  6. vizpal

    Does modelsim support systemverilog simulation now?

    modelsim questa option Questa would be a Verification Specific Tool from Mentor ... :idea:
  7. vizpal

    Can anyone send the open verification methodology docs?

    ovm concepts Basic Document !!! Start with OOP's -> System Verilog -> AVM or TLM or VMM or RVM and then -> OVM . This is the best way to understand OVM. U must have strong understand with concepts of classes and concepts of polymorphism, abstract classes, virtual classes.... Once u kinda...
  8. vizpal

    functional and formal verification

    +functional verification is +rtl Functional Verification is checking your DUT's behaviour on different inputs combinations... Formal Verification is checking different possible States covered by you DUT...
  9. vizpal

    Looking for Synopsys Verification Methodology Manual

    Re: VMM Material Synopsys VMM !!! "Verification Methodology Manual"... Similar to AVM but not open source ... Okey, whats abt this VLM ?? Is it something similliar ???
  10. vizpal

    Looking for Synopsys Verification Methodology Manual

    Hi Guys, can anybody share soft copy of vmm training if possible !!! It wolud be of great help... Thx in advance :D
  11. vizpal

    "one-hot" and "zero_one-hot"

    What is the advantage of using one-hot when zero-one-hot has one FF less?? Most state machines are built around either one of these.. !!! Any specific application were to use one-hot and zero-one-hot ??? :!:
  12. vizpal

    Synopsys's VMM and Mentor's AVM

    VMM and AVM are both class bases verification methodologies... VMM is not open source, but AVM is open source !!! AVM makes use of TLM concepts for communication between testbench blocks while VMM makes use of much raw mailboxes and stuff... But, both have there pros and cons !!! You can also...
  13. vizpal

    "one-hot" and "zero_one-hot"

    Whats the difference between "one-hot" and "zero-one-hot" ??? Give examples, Please..... !!!:| Thx
  14. vizpal

    What's the best VHDL/Verilog/SystemVerilog editor?

    ultaredit vhdl I have been stuck with GVIM for a long time !!!! :D
  15. vizpal

    How "One - Hot" encoding make data path short.

    State transitions are less....
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