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Recent content by vivek keviv

  1. V

    xilinx FIR compiler IP core

    I am sorry about that.. I have entered below about error lines.. here line 57 and 66 tells fircompiler and fircompiler_q module instantiation.... Can you please tell me the error "unsupported target" Error lines: ERROR:Xst:872 - "band_pass_filter.v" line 57: Unsupported target...
  2. V

    xilinx FIR compiler IP core

    Hi, I am trying to design a band pass FIR filter using fir compiler IP core generator. I have entered the filter coefficients, sampling frequency, clock frequency and all other parameters. Once I created the core module I have instantiate the core to the top module. when I try to synthesize it...
  3. V

    Regarding help in instantiating Xilinx IP CORE GENERATOR in verilog

    Hi Thanks for your valuable time. Without using Xilinx IP Core module, I can able to get the results but when i try to instantiate IP core with my verilog LPF code I couldn't able to get the results. I believe that there may be some problem due to this XST 616 warnings. I have googled this...
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    Regarding help in instantiating Xilinx IP CORE GENERATOR in verilog

    Hi, I am working with USRP-FPGA. I would like to build my own custom fpga image into my USRP-FPGA. Here my custom fpga image is Low pass FIR filter. when I tried to wirte and synthesize my low pass filter verilog code with Xilinx IP core generator, it shows some XST tool warnings something...
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