xilinx FIR compiler IP core

[vivek keviv]

Hi,

I am trying to design a band pass FIR filter using fir compiler IP core generator. I have entered the filter coefficients, sampling frequency, clock frequency and all other parameters. Once I created the core module I have instantiate the core to the top module. when I try to synthesize it show error as unsupported target.

I have attached my codes below. can you please kindly advise me how to solve this probem??

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Code Verilog - [expand]
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module band_pass_filter(
    input clk,
    input reset,
    input in_strobe,
    input out_strobe,
    input [31:0] Xinput,
    output reg [31:0] Youtput
    );
     
wire [31:0] out_FIFO;  // to store and split the signal as inphase,quadrant
wire is_full, is_empty;
 
// declaring input inphase and quadrature components
wire signed [15:0] i_input=out_FIFO[31:16];
wire signed [15:0] q_input=out_FIFO[15:0];
 
// declaring output inphase and quadrature components
wire signed [31:0] i_output;
wire signed [31:0] q_output;
reg clock_enable;
reg s_clr;
 
fifo_bpf fifo_generator (
  .rst(reset), // input rst
  .wr_clk(clk), // input wr_clk
  .rd_clk(clk), // input rd_clk
  .din(Xinput), // input [31 : 0] din
  .wr_en(1'b1), // input wr_en
  .rd_en(1'b1), // input rd_en
  .dout(out_FIFO), // output [31 : 0] dout
  .full(is_full), // output full
  .empty(is_empty) // output empty
);
 
 
 
fircompiler my_fir_compiler (
    .sclr(s_clr), // input sclr
    .clk(clk), // input clk
    .ce(clock_enable), // input ce
    .rfd(1'b1), // output rfd
    .rdy(1'b1), // output rdy
    .din(i_input), // input [15 : 0] din
    .dout(i_output)); // output [32 : 0] dout
 
fircompiler_q my_fir_compiler_q (
    .sclr(s_clr), // input sclr
    .clk(clk), // input clk
    .ce(clock_enable), // input ce
    .rfd(1'b1), // output rfd
    .rdy(1'b1), // output rdy
    .din(q_input), // input [15 : 0] din
    .dout(q_output)); // output [32 : 0] dout
 
always @(posedge clk) begin
    if(reset) begin
    Youtput <= 0;
    end
    else if (out_strobe) begin  
    Youtput <= {i_output[30:15], q_output[30:15]};
    clock_enable <= 1;
    s_clr <= 1;
    end
    end
 
endmodule

---

error:

ERROR:Xst:872 - "band_pass_filter.v" line 57: Unsupported target.
ERROR:Xst:872 - "band_pass_filter.v" line 57: Unsupported target.
ERROR:Xst:872 - "band_pass_filter.v" line 66: Unsupported target.
ERROR:Xst:872 - "band_pass_filter.v" line 66: Unsupported target

 

[vivek keviv]

I am sorry about that..

I have entered below about error lines.. here line 57 and 66 tells fircompiler and fircompiler_q module instantiation....

Can you please tell me the error "unsupported target"


Error lines:

ERROR:Xst:872 - "band_pass_filter.v" line 57: Unsupported target.
ERROR:Xst:872 - "band_pass_filter.v" line 57: Unsupported target.
ERROR:Xst:872 - "band_pass_filter.v" line 66: Unsupported target.
ERROR:Xst:872 - "band_pass_filter.v" line 66: Unsupported target

 

[FvM]

You didn't report the correct error lines. I guess they are in fir module instantiation.

- - - Updated - - -

I asked about showing the error lines in the posted code, not repeating the error message.

Each error refers to a specific assignment. Find the assignments and consider why they violate Verilog syntax rules. Has to do with things like wrong vector size or wire versus reg usage. You might also browse the Xilinx help for a general explanation of the error message.

 

[mrflibble]

Are you sure the code you post is the entire file? Because error on line 57 and 66 seems a bit strange, especially line 66.

 

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57   .rfd(1'b1), // output rfd
58    .rdy(1'b1), // output rdy
59    .din(i_input), // input [15 : 0] din
60    .dout(i_output)); // output [32 : 0] dout
61 
62 fircompiler_q my_fir_compiler_q (
63    .sclr(s_clr), // input sclr
64    .clk(clk), // input clk
65    .ce(clock_enable), // input ce
66    .rfd(1'b1), // output rfd
67    .rdy(1'b1), // output rdy

If the comments are correct then assigning 1'b1 to rfd and rdy is incorrect and will result in the error Xst:872 as 1'b1 is an invalid target for an output. Remove the 1'b1 from all four locations i.e. you can use .rfd(), for unused outputs in an instantiated module.

I suspect the OP cut and pasted the same line number twice as it should have been:

ERROR:Xst:872 - "band_pass_filter.v" line 57: Unsupported target.
ERROR:Xst:872 - "band_pass_filter.v" line 58: Unsupported target.
ERROR:Xst:872 - "band_pass_filter.v" line 66: Unsupported target.
ERROR:Xst:872 - "band_pass_filter.v" line 67: Unsupported target