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Hi instead of using the constraint editor try to have an constraint file if you check the xilinx website on topic of constraints you will find that there are certain command formats to be followed in the constraint file such that you force the file to behave in the way you want it .
hope this helps
Hi ,
In communication system you find that coding is followed by Modulation . Following this if i try to use the manchester coded wave to PPM modulator . You find that the modulator converts the manchester code d wave back to the normal ones and zeroes before modulation . This makes the...
Hi just some knowledge on this
lets take the case of PPM in your case we have 3 bits so there are 2^3 -1 possible values that can be represented . Now all these 7 will be representes as each position in pulse . ie say we have a pulse of 1MHZ that is 0- 1 Us(makes one slot )in this o.1 us will...
Hi I am a new bee
I need to how is the sync between two clock domains is done .
How can i design it using VHDL without using the Async FIFO .
if anybody has a generic code please pass on to me
with regards
kewl
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