Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by vinod_cheedella

  1. V

    AMBA AHB Presentation

    nice material with brief summary...
  2. V

    The Verification Language trend is Systemverilog

    can you specify your experience on VCS and why you think its buggy tool ?
  3. V

    Tools that Support "System Verilog Assertions"...?

    Re: Tools that Support "System Verilog Assertions" synopsys support sv, including assertions also, but i don't think so, VCS works over windows plotform...
  4. V

    help to learn SystenVerilog

    here is a link to start with System Verilog... https://www.asic-world.com/systemverilog/index.html
  5. V

    How to read one line at a time from a file in Verilog?

    Re: verilog file read $fgets(line,fd); will read line by line from the file descriptor "fd", and stores in the reg vector "line". one thing is that, you should be careful in declaring the width of the reg_vector "line". such, that the width should be more enough to store the line.... i think...
  6. V

    [VMM:QUESTION] What's the difference with peek and get?

    blocking get in vmm_channel .get() will take out the data from the channe, .peek() will just take the copy of the data, both the tasks are blocking, stops simulation unless the channel is again having atleast one data member. if the channel is empty, and if you are doing .get() on that...
  7. V

    Script for sending email with attachment using Linux console

    Re: mail using perl did u you use mail -- the shell command... or use Mail::Sendmail module in perl.....
  8. V

    System Verilog Random Seed Variation

    systemverilog random seed srandom(int seed) is the key to have manual seed.... class packet; rand bit [7:0] header; function new(int seed); this.srandom(seed); endfunction endclass initial begin packet p=new; p.new(33); end
  9. V

    Vera to System Verilog

    if you are working only on verification side, means you are always writing test bench prorams, then vera is ok, if you do write both the design and test benches, it better to adopt the system verilog. you can have design as well as test bench constructs in system verilog. i feel, nothing...
  10. V

    data structures and algorithms

    hi, i am attaching the .c file for the above program, try this program, if it solves your problem, its ok, other wise let me know, i will change this again..... #include<stdio.h> int main () { typedef struct {int marks; int year;}Struct; Struct Array[10]; int...
  11. V

    Help me build a System Verilog verification environment

    Re: ** SYSTEM VERILOG ** hi Ankith, declare this unwanted variable "goodcrc" outside the class scope, lets say in program scope. ok, now in the post_randomize() function do randomize this goodcrc like goodcrc=$random, and remaining things are as before.. class methods can see the signals...
  12. V

    data structures and algorithms

    Hi, there are many ways to solve this problem.. ok, let me explain one way for this.. 1. Take an array of structures, lets say of size for example 10... structure should consists of two fields a. "year" to which the student belongs to b...
  13. V

    What is the importance of PERL language for VLSI design engineer?

    Re: perl Yes, Perl is a very good handy tool for your work, irrespective of design or verification.. once you learn the basics, you can minimise your work. there is a topic in perl, Regular Expressions does a lot for the automation. Basically Perl is mostly used for Text processing as far as I...
  14. V

    Help me build a System Verilog verification environment

    Re: System verilog---- vcs-2006-06 version supports constraints "randomize" i think so, by defualt they work in program scope....
  15. V

    Help me build a System Verilog verification environment

    Re: System verilog---- hi ankit, try vcs 2006-06 version, it supports most of the SV features, constraints and many more which are very helpful for verification environment. better try to check with your administrator regarding the latest version of vcs available. anyways, please let me...
See more

Part and Inventory Search

Back
Top