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Recent content by vikasjn

  1. V

    constrains in the sythesis

    pls check the discussion - " How to write a script for synthesis" In that i have uploaded a pdf ... dctut.pdf download that ..it is enough for starters .. it also will tell u about common constraints in synthesis
  2. V

    difference between design compiler and prime time

    DC is a synthesis tool while PT is a static timing analysis tool ... what does it exactly mean ...the post above give u a genral idea ... ok it is true that DC also has a internal STA engine that is not directly controllable ... dc uses it for it's own analysis ... selfish!! ...The other thing...
  3. V

    How to write a script for synthesis

    ok i think i get the picture ... I am assuming u use DC if not tell me which tool u r using... this is a old synopsys tutorial ..dono why they discontinued giving it ... used it long back .. the source files required for this are still distributed by synopsys (never understand these EDA guys) ...
  4. V

    Calling tasks hierarchically in Verilog

    Re: calling tasks in verilog Ya , u can call a task from anywhere hierarchially... the code u are referring to deals with the event emission ... please go through this section in any verilog book u will find the required information .
  5. V

    Problem with results of synthesizing with two frequencies

    Re: Synthesis problem please recheck ur wire load model u may be using a very pessimistic ... or may have gone for overkill ... usally it is the other way around !!! I am assuming that all other constraints remain the same :)
  6. V

    timing closure for a design operarting over a range of frequ

    Re: timing closure for a design operarting over a range of f Typically u choose the mode which is most used (usally called mode independent) .... try closing ur design here then do a STA on all the modes and check if it is ok in all modes ... if u find that it does not work in a particular mode...
  7. V

    Problem with port defined as inout in a module (Verilog)

    Re: Question on Verilog assign ur register to a wire and connect this port to a wire ... but make sure u r driving Z when u don't want to drive any value!!!!
  8. V

    How to write a script for synthesis

    ok sir, First understand the essence of synthesis ... get the basic right the rest will fall in place :) ........... Next decide on whether u are calling ur cards on FPGA or ASIC synthesis tool .... if u have absoultely no idea on what the whole thing is ... i would suggest u start from xilinx...
  9. V

    How to begin learning specman and e language ?

    how to write specman Well u could try to go through Specman tutorials provided along with the tool .B ut the best way to learn ... if u have no idea about Object Oriented Programming at all is through the text book ... Design veification in e -sameer Palnitkar ... i Belive e-book format for...
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