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Hi
These are like fundamental stuff, It would be helpful if someone can provide a tutorial sort, a detail explanation with examples...will be of great help to me
Thanks in advance
Venkat
VHDL code for UART
Hi all
I am doing project on uart 16550. Can some one please share the design details or specification document.
Thanks in advance
venkat
Hi
@ray123
if my 8 bit reg has 01110000
then I should get '0' as output
But ur solution gives '1'
@shanmugaveld
ya 2 4-bit full adders will do.
but can it b more simple.
digital circuit and design interview question
Design a combinational circuit which gives high output when any 2 bits of 8 bit register are high. Can that be extended such that 3 bits 4 bits...etc
authentication rejected cadence
Hi
I have successfully installed IC610 and MMSIM61 on fedora 8
But I could not simulate any design, because there are no libraries.
It says there is no cds.lib (I am new to this tool)
I got NCSU CDK 1.5 and Installed it following the instructions from pdf(below)...
Hi
Problem 1
Extracting InstallScape version for platform lnx86 in / opt / InstallScape
./SETUP.SH: line 814: uncompress: command not found . / SETUP.SH: line 814: uncompress: command not found
Starting up InstallScape in GUI mode Starting up InstallScape in GUI mode
DISPLAY...
rtl to gds
Hi everybody !
I am doing an ASIC project, I have RTL coded that and got Synthesized netlist using MGC tools.
Now I have MMI SUE and MAX. I am facing difficulty in interfacing these two even though MMI has 'ediftosue' and 'verilog_to_sue' scripts.
Is there some source which explains...
synopsys dc 2008 install
Hello all
I have problem installing Synopsys DC
I have Synopsys DC 2005.09-sp4 version, tried installaling on fedora 8, got the following error.
ERROR : Failed to execute /uar/synopsys/X-2005.09-SP4/admin/install/syn/bin/install_psyn
Could some one help me to solve...
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