Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by venkateshr

  1. V

    whats wrong with this current source

    generally current sources can be classified into two things. current source and current sink. former is sourcing current to bottom circuitry while the latter sinks some definite amnt of current. pmos /pnp is the candidate for source and nmos/npn is the candidate for latter as current value...
  2. V

    question of comparator

    this technique is widely used in digital logics where you need to drive large cap loads. instead of making one large inverter(it offers large capacitance to the previous driver )which starts slowly ,they make small inverters(scaled in G.P) to drive the cap. to reduce the time delay. u can...
  3. V

    why we don't consider about group delay in analog design?

    Re: why we don't consider about group delay in analog design so the phase remains constant over the narrow Radio frequency band of interest instead of linear decrement as in ordinary case. can the 3-db frequency be lesser than this band and I introduce a zero in the band where my RF lies. can...
  4. V

    Applications of NMOS transistor

    Re: NMOS TRANSISTOR as amplifiers where the load is any resistor or another nmos (if not pmos)
  5. V

    why we don't consider about group delay in analog design?

    Re: why we don't consider about group delay in analog design well the speed is the reason. we should go for maximally flat response to get delay(transient)-bandwidth(ac) balance. if there is peaking u may have better bw but the delay will be more than the circuit without the peaking. in normal...
  6. V

    [SOLVED] Help me choose a better buffer for op-amp

    Re: help in opamp Left one is better for the following reasons 1) Low output impedance 1/A*Gm || R =1/(A*Gm) and for right it is 1/Gm || R 2)High resistance to power supply variations (calculate ,it will be A*Gm*Ro*R) for right it will be Gm*Ro*R 3)Not that sensitive to output change as...
  7. V

    What is the significance of 3-db bw?

    Re: 3-db bw thanks Ian. i know how the 3db comes and what the output res. wil be and the load impedance will be equal to output reasistance. all i know but i dont know why we insist on 3-db bw. is that bbecause we want freq. reponse devoid of any pole
  8. V

    What is the significance of 3-db bw?

    what is the significance of 3-db bw. i know much about that but dont know why all insist on that rather than say 0-db bw. is that due to consitent gain or phase diff. plz explain me
  9. V

    high swing current mirror?? please help me ..

    diode connected transistor saturation equation thats right shake but the currents will be matched between the right and left arm as the feedback will make sure that the currents are equal (proportional) I am quite sure that it is 100% matching and we need to tweak the bias to have the magnitude...
  10. V

    high swing current mirror?? please help me ..

    current high swing again the difference in vds drop is also accounted and hence very perfect matching is obtained
  11. V

    high swing current mirror?? please help me ..

    high swing current mirror HI all , Left hand side is the first order high swing cascode mirror . U can see the bias for the top transistor and the second bias is provided by that ckt itself. Ckt on the right side is used for better matching and to avoid the bodf effect faced by the...
  12. V

    Analog signal level shifting

    opamp summer will do this . u can implement switched capacitor summer also. i
  13. V

    Testing open loop gain of fully differential CMOS op amp

    give a known -ve feedback of say β . O/p= I/P * A /(1+AB). give ip so that op doesnt saturate only A is unknown u will get that thru the above eq. Added after 1 minutes: i assumed common mode gain is negligible . again if u want to find that do the normal case by applying a common mode...
  14. V

    questions on bandgap, please help me.

    instead of that laborious thing u can introduce a source follower and a resistor didvider like stuff to have the shift/gain from 1.13 to 1.25. in simple words a buffer as said b4
  15. V

    Cmos Voltage Reference

    it could be that they use the sub threshold region of MOSFET where the diode connected mos really behaves like a diode which can be used to generate iptat a and ictat.

Part and Inventory Search

Back
Top