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Recent content by Vabzter

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    creating instances in cadence virtuoso

    Hi, The easiest way is to open Virtuoso from Composer window. Tools-> Design Synthesis -> Layout XL. Then from Layout XL got to Design -> Gen from source. Lets say you have an inverter in the Schematic window. After you do Gen from source it will place 1 NMOS and 1 PMOS and all i/o pins...
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    how do I measure transister area and Vt mismatch in cadence?

    Re: how do I measure transister area and Vt mismatch in cade Hi, You can refer a paper on transistor mismatch by Pelgrom. Generally mismatch = const/sq.rt(area) You have to look into your process manual to find out this value for the constant. BR Vab
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    [SOLVED] The concept virtual ground in op-amps

    Re: Virtual ground Hi, In case of a differential amplifier when you give pure differential signal to the inputs then one voltage on the gate is increasing and the voltage on the other gate is decreasing. The point where the sources of both the transistors are connected remains same. Hence...
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    How to add pads in gpdk .18um tech?

    Hello everyone, I have created the layout of an Opamp in Cadence Virtuoso using GPDK 0.18um technology. I have created the contacts for i/p o/p vdd and gnd. How can I add a pad structure to it? Thanks and regards, Vabzter
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    Beginner:Problem in Adding Instance in virtuoso Cadence.Help

    Re: Beginner:Problem in Adding Instance in virtuoso Cadence. hi the best tutorial is by Cadence itself. It is very comprehensive and useful..
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    Where to find tech file in cadence?

    Answer the following questions first: 1. What technology you are using? 2. Can you post the names of all the files in your Library manager?
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    Beginner:Problem in Adding Instance in virtuoso Cadence.Help

    Re: Beginner:Problem in Adding Instance in virtuoso Cadence. Many thanks for your response Amarnath . I understood this thing from you. Hi, Create a new library. Whe u create it a new window pops up with 3 options. In that select "Attach to a tech file". You get a list of all libraries in...
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    Why is precision rectifier called this way?

    Re: precision rectifrier To rectify signals less that 0.6V like signals from a sensor e.t.c which may be in mV. A normal rectifier like bridge will not work as the signal is less than threhold of the diodes.
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    rail to rail opamp...urgent need help

    Hi, You have a pair of differential input stage- the PMOS in the left and then followed by NMOS. Rail to Rail means that full swing from 0 to Vdd. Hence u need to have a parallel of NMOS and PMOS stages at input. You need current source to have proper constant current in the input which...
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    Help me design an opamp for the output of DAC

    Re: Opamp Design Help.. Hi, No what I meant was that the input to opamp is 0 to 1.2V and the output of opmap should be 0 to 1.75V. The opamp is directly connected after DAC whose full scale output is 1.2V. Thanks Vabzter
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    Help me design an opamp for the output of DAC

    Re: Opamp Design Help.. Hi Thanks for all the replies..What what I undustood I can have a simple 2 stage with Class AB as an output stage. Is this correct? Also can someone post some links/papers for class AB CMOS design..That would be very helpful tome. Thanks Vabzter
  12. V

    Help me design an opamp for the output of DAC

    Hi all, I have the following specs and I want to design an opamp. The application is that it should be connected at output of DAC and amplify from 1.2(full scale o/p of DAC) to 1.75 V. So will connect it in non inverting configuration.. Vcc=1.8V Vout=1.75V Cl = 35pF, Rl = 5Kohms Idc...
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    basic question, fall time measurement with cadence ic calc

    how to obtain fall time in cadence Hi, I have not tried this and not sure but if u change the percent low value as 90% and percent high as 10% in rise time then u can get fall time.. see if you can get the result by this way.. BR Vabzter
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    Hi, How about your design method?

    Hi all, Excellent post from all. but i have one question.lets take a simple 2 stage opamp for design..in my univ they gave us a datasheet of 0.35um process(un, cox, vth e.t.c) Buts lets say in a company where u are designing for 90nm for less, then do u still find these process...
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    Help for ladder type DAC..

    Hi all, I am designing a 10 bit resistive ladder type DAC. It has 2 resistive ladders, one for MSB and other for LSB. To have a good matching I have constructed the MSB ladder in terms of LSB unit resistor i.e 1 Lsb unit resitor = 234 Ω and 1 msb resitor is 32 * 234 = 7.5KΩ Has...
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