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Recent content by urmish

  1. U

    Metastability in flops not too many engineers can answer.

    it would be naive to not consider how the chances to chip failing due to metastability issues are so low that it would be worthwhile to look into other aspects of design and manufacturing. Nothing in a chip design is perfect. Even in DFT we learn that coverage of 100% is an NP complete problem...
  2. U

    Clock divider by 3 with 50% duty cycle?

    Re: clk divider 3 the best way and glitch free way is mentioned here ASIC Verification: Clock Dividers For the lazy ones I have quoted the text below The easiest way to create an odd divider with a 50% duty cycle is to generate two clocks at half the desired output frequency with a...
  3. U

    Frequency Doubler circuit

    this was a question in last years final exam check out the circuit in the first question. It was used in the Pentium 4 design. My college professor was actually a design engineer at Intel for 5 years
  4. U

    Literature needed on Static timing analysis

    This is one of my favorite links for a beginners guide to STA STATIC TIMING ANALYSIS also weste harris has some pretty cool slides on two phase clocks, pulsed clocks, edge triggered flops and setup/hold/time borrowing here **broken link removed** go to sequential circuit design
  5. U

    Metastability in flops not too many engineers can answer.

    we basically reduce the probability of occurrence of metastability by using double flip flops back to back. If you look at the MTBF(inverse of probability. Well not exactly but will be good for answering your question)equation for a synchronizer, you can easily verify for yourself that the...
  6. U

    dftadvisor help (urgent)

    Hi, I am trying to insert partial scan into my design of a processor (gate level net-list), but the tool says "Error: ATPG based scan identification is no longer supported" However the other 4 types namely full_scan clock_sequential sequential_transparent wrapper_chains seem to work fine...
  7. U

    How to fix clock capture ability check violation in dft advisor?

    have you added the command add clocks 1 reset that should not come along with add clocks 1 clk
  8. U

    nature of a cpu design internship

    hi guys i have used this forum a lot for preparing for digital design interviews and learning many concepts in asic design. i have secured an intern in a cpu design team in a leading semiconductor company. But I still do not know what exactly is expected from an intern and the nature of his...
  9. U

    what is useful skew.how will come useful skew?

    very helpful doc thanks
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