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Hi,
should be possible to reach a 100% code coverage;
as said in another reply, teoretically each line of the code has been coded for a reason; with the testebench is possible to setup the correct test case to stimulate a particolar line of code.
An exception can be the lines are NEVER executed...
Hi Alanray, using 2 clocks input you increase the coverage because you check the connection between clock domains. Finaly I have set it up and it worked well! For me is better to avoid latches and user two o more clocks input during scan.
HI all,
has any one experience in using FASTSCAN for scan pattern generation in a design where there are 2 (or more) clock domains.
I want to pulse syncronously the two clocks during shift; then pulse sequestially in the capture phase.
In this way it is possible to check also the connections...
Hi, here we use standard unix SCCS.
If fast handling large files.
Depending of your platform, maybe you can use the gnu version (look in h**p://cssc.sourceforge.net/ ).
Hi, I worked with both these languages.
I started (5 years ago) with verilog. Verilog is veri easy to learn.
Now I´m using VHDL. Whith VHDL ,for me, is easier to manage large project (developed by more than 1 person), and is more difficoult to insert erros in the code. VHDL is also enough...
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