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Recent content by UFK

  1. U

    MATLAB help required for Image Processing!

    Hello Thanks for the response. Im working on the SPIHT Image Compression Algorithm. Iv calculated the DWT of a sample image on MATLAB, then designed the encoder and decoder on Verilog HDL. The decoded output is a 16X16 matrix on which i want to perform the Invserse DWT so i can recover the...
  2. U

    implementing DWT and SPIHT compression on FPGA

    Maybe the following link can help MATLAB Central - File detail - SPIHT
  3. U

    MATLAB help required for Image Processing!

    hi all im trying to perform a 4-level Inverse discrete wavelet transform by using the MATLAB command idwt2, on a 16x16 matrix. Please help me with it. Thanks alot in advance
  4. U

    IDWT in MATLAB. Please help

    Dear All Im trying to calculate the 4-level Inverse DWT of a 16x16 matrix and then map the resulting matrix after the 4-level idwt2 in an image form. Can someone please help me with it? Thanks in advance
  5. U

    VHDL source code for EZW or SPIHT algorithms

    do u still need the matlab code cuz i can help you with it.
  6. U

    [SOLVED] Correction required in Verilog Code

    Thanks phoenixpavan I tried the suggestions on that forum and neither didnt work for me :((((
  7. U

    [SOLVED] Correction required in Verilog Code

    Im using a Spartan 3E Xilinx device and my software version is 11.3. My encoder code uses the $readmemb task and is synthesizing fine. I have no idea what im doing wrong in my decoder code. Im not very good at Verilog so its hard to figure out my mistake. Thanks for replying
  8. U

    [SOLVED] Correction required in Verilog Code

    Dear Verilog Users Im posting a portion of my code for a compression decoder. It gives me no syntax error but when i try synthesizing it gives the following error: INTERNAL_ERROR:Xst:cmain.c:3446:1.47.6.2 - To resolve this error, please consult the Answers Database and other online resources...
  9. U

    [SOLVED] Verilog synthesis problem!Please Help

    Thanks Fvm. I understand what you suggested and i tried it in my code. It gives correct results and synthesizes too. But it just gives a 96% Bonded IO result and 0% slice utilization which leads me to think there is a problem which the simulator cant comprehend. Im posting my code and...
  10. U

    [SOLVED] Verilog synthesis problem!Please Help

    Hi paulki Thanks for your help. I tried what u suggested and my code calculates the value correctly but it still does not synthesize. I gave a constant value to the variable 'i'. It gives me the same error which is ERROR:Xst:2634 - "Log_max.v" line 37: For loop stop condition should depend on...
  11. U

    [SOLVED] Verilog synthesis problem!Please Help

    Dear Verilog users Please help me synthesize a simple Verilog program which calculates the log base 2 of a value. My code is The testbench is If i use the datatype reg for variable 'i' the program synthesizes but does not give results. Please help me synthesize this code. Thankyou
  12. U

    [SOLVED] how to calculate log2(n) in verilog

    Dear meher81 I need you help. Im posting a code which u wrote for me a few months ago. Its a part of my encoder. It just wont synthesize. Maybe you can help. The code is Testbench It gives correct result but cannot synthesize. Please help Thankyou
  13. U

    Moving or deleting array elements in Verilog!

    Hi All I have found out that System Verilog permits manipulating array elements by moving array elements from one element to another and deleting elements too. Does regular Verilog have this option? In my code, under a certain condition one array is supposed to move a few of its elements to...
  14. U

    [SOLVED] Reading negative hex values in Verilog!Plz HELP

    Thankyou so much. I tried what u suggested but it still wont work correctly for neg values. I am posting my code below along with the text file its supposed to read. Perhaps you could run it to see what can be fixed in it. 1. This code should compare text file values with the constant T. 2...
  15. U

    [SOLVED] how to calculate log2(n) in verilog

    Dear meher Maybe you could solve another one of my neverending problems. Im posting my code below. If possible, Please run it and see if it can be altered to function the way i want. My code isnt reading negative hex values. It only gives correct results for positive hex values. Can anything be...
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