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Recent content by u24c02

  1. U

    AXI FIFO does not work

    Dear all, Now I'm trying to implement with axi4lite FIFO in the vivado. I add 3 IPs, one master, one interconnection, axi4lite FIFO. The problem is that Fifo does not write and read when I tried write and read. Here is waveform. Would you please let me know what should I do to solve this...
  2. U

    the problem of Axi4 Lite BReady does not asserted in the xilinx Vivado.

    Thanks, I'm confused after read the document, then the fifo does not follow axi interface?
  3. U

    the problem of Axi4 Lite BReady does not asserted in the xilinx Vivado.

    Hi. I'm trying to implement the fifo in the vivado. the fifo which is based on axi4 lite prtocal. I just made one maser and interconnect and fifo_generator. The problem is that I issue the awaddr and wdata and checked awready and wready but Bready does not asserted in the progress. Does...
  4. U

    [mv] how to compile VHDL in error library unisim; logical library name must be mapped

    Now I'm trying to implement with FIFO which is based on AXI4LITE in the zynq system. But as I know, the general fifo has write and read and clock ports. But this case, absolutly different. They are connecting with AXI4. The problem is that I don't know why the master need to read like araddr...
  5. U

    [mv] how to compile VHDL in error library unisim; logical library name must be mapped

    Hi. Now I'm trying to compile with VHDL files. but I got some error messages when I compiled with that VHDL file. Does anyone know how to handle of this? library unisim; | ncvhdl_p: *E,LIBNOM (koko_fifo_exdes.vhd,68|13): logical library name must be mapped to design library use...
  6. U

    how to control xilinx axi4lite fifo?

    First of all, I want to get your" fifo_generator_vlog_beh.v" files. It seems that you get some verilog files from coregen. So Would you let me know what kind of tool and version you used to get that verilog files? Is this a fifo right? And AXI4 interface type? - - - Updated - - - Thanks my...
  7. U

    how to control xilinx axi4lite fifo?

    Can you let me know what you have a tool version? - - - Updated - - - How can you get as verolog? As I know Xilinx LogiCOREIP FIFO Generator is support vhdl not verilog.
  8. U

    how to control xilinx axi4lite fifo?

    Thanks ads-ee, yes I knew that, but My fifo generator testbench has only vhdl version. Also the problem is that I'd like to control in the bus vivado bus architecture. So I need to know how to control that IP on the zynq vivado system. Firstly I'll check how to get verilog version. My coregen...
  9. U

    how to control xilinx axi4lite fifo?

    Hi. I'm looking for some tutorial or example to control AXI4LITE FIFO. I'm familliar with native fifo but AXI4 does not. So I'm looking for some example about how to control AXI4LITE FIFO of the xilinx. Can you help me please? I just make one fifo then there is S_AXI and M_AXI port. I don't...
  10. U

    Master and slave address relationship in the AXI4LITE

    Hi. Basically, as i know, one master can access all slave address map. For example, what if we have 1 master and 2 slave, then the master can access 2 slaves. But in the AXI4-Lite, is this methodology supporting? Or should I have to make 2 master to control 2 slave each by each?
  11. U

    What kinds of tools are used to xilinx FPGA engineers?

    Currently, my company has any tools except vivado(not including bfm license). So I'd like to request to my company to buy some tools like VCS or IUS or modelsim. Unfortunately, IUS is very expensive. So the choise options go narrow.
  12. U

    What kinds of tools are used to xilinx FPGA engineers?

    Thanks, how about your case? If you don't mind would you let me know a little bit?
  13. U

    What kinds of tools are used to xilinx FPGA engineers?

    Hi. I'm just wondering about what kinds of tool does zynq Xilinx FPGA engineer use? Just only vivado or something else?
  14. U

    [SOLVED] What is the best approch to connect between each other fpga board?

    Thanks but they have each resister map and need to 40MB/s over. Is there any good communication protocol between each other?
  15. U

    [SOLVED] What is the best approch to connect between each other fpga board?

    Hi, I'd like to connect to 3 fpga board but those fpga boards are moved away about 3 meter. In this case, I'd like to know which the connection methodologies are better approch. 1 zynq board 2 atrix boards Star connection between them.
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