[mv] how to compile VHDL in error library unisim; logical library name must be mapped

[u24c02]

Hi.

Now I'm trying to compile with VHDL files. but I got some error messages when I compiled with that VHDL file.

Does anyone know how to handle of this?

library unisim;
             |
ncvhdl_p: *E,LIBNOM (koko_fifo_exdes.vhd,68|13): logical library name must be mapped to design library
use unisim.vcomponents.all;
         |
ncvhdl_p: *E,IDENTU (fifo_exdes.vhd,69|9): identifier (UNISIM) is not declared 
ncvlog: *F,WRKBAD: logical library name WORK is bound to a bad library name 'work'.

and the below is run script.

mkdir work

echo "Compiling Core Verilog UNISIM/Behavioral model"
ncvlog -WORK work fifo.v
ncvhdl -v93 -work work fifo_exdes.vhd

 

[ads-ee]

Unless the Xilinx libraries are pre-compiled (not the case in the full version of the tools) you need to run the library compilation script Xilinx provides.

Also mkdir work is unlikely to be the way you create a library in ncvhdl, simulators usually require you use some specific library creation command to do this, e.g. vlib work for Modelsim.

- - - Updated - - -

Here this might help you set things up properly to compile your design.

- - - Updated - - -

And here is an AR on compiling Vivado libraries in NCsim.

 

[u24c02]

Unless the Xilinx libraries are pre-compiled (not the case in the full version of the tools) you need to run the library compilation script Xilinx provides.

Also mkdir work is unlikely to be the way you create a library in ncvhdl, simulators usually require you use some specific library creation command to do this, e.g. vlib work for Modelsim.

- - - Updated - - -

Here this might help you set things up properly to compile your design.

- - - Updated - - -

And here is an AR on compiling Vivado libraries in NCsim.

Now I'm trying to implement with FIFO which is based on AXI4LITE in the zynq system.
But as I know, the general fifo has write and read and clock ports. But this case, absolutly different.
They are connecting with AXI4.

The problem is that I don't know why the master need to read like araddr, rdata..? also why the slave need to write, awaddr? I'm not asking you the axi's interconnect ports. I already know that. My question is, in especially this case, the purpose of them.


I don't understand it , what is the purpose that ports in this case?

I know, even the fifo have the testbench. I already ran about the testbench of the FIFO but it's getting to hard understand.

Can you let me know more easy example?