What kinds of tools are used to xilinx FPGA engineers?

[u24c02]

Hi.

I'm just wondering about what kinds of tool does zynq Xilinx FPGA engineer use? Just only vivado or something else?

 

[shaiko]

It depends,
If you're designing the logic then Vivado is all you need (including all the inner plugins you may or may not require).

 

[u24c02]

It depends,
If you're designing the logic then Vivado is all you need (including all the inner plugins you may or may not require).

Thanks, how about your case? If you don't mind would you let me know a little bit?

 

[shaiko]

I mostly implemented logic on the Zynq's PL that talks with the PS and sends data over a high speed link to another FPGA.
Used only Vivado and Modelsim.

 

[vGoodtimes]

I feel that most design houses use:

Vivado + Modelsim + (editor), and possibly synplify as a synthesis tool. Python for useful things and TCL for garbage that has to work with Vivado. bash as a useful shell, and tcsh as a terrible shell.

(I hate TCL.)

 

[shaiko]

I hate TCL

u24c02,
If somebody hates something - then it's probably because he spent hours/days to try to make it work.
And if he was willing to spend hours and days despite the suffering - it means that this something was important enough to suffer for.
Therefore, you should definitely add TCL to your "to learn" list.

 

[u24c02]

I mostly implemented logic on the Zynq's PL that talks with the PS and sends data over a high speed link to another FPGA.
Used only Vivado and Modelsim.

Currently, my company has any tools except vivado(not including bfm license). So I'd like to request to my company to buy some tools like VCS or IUS or modelsim.
Unfortunately, IUS is very expensive. So the choise options go narrow.

 

[vGoodtimes]

No. TCL is something that was developed by HW engineers in the late Nineteen Hundred and Eighties and now tool vendors think HW engineers want it. (and i understand the original motivations and feel the original intent was good.)

It is more likely a new HW engineer will already know python before being forced to look at TCL. But vendors don't care. In my opinion TCL is "The Cancer Language" at this point. It isn't going away and it is terrible. But tools aren't written by the people using the tools.

 

[TrickyDicky]

Vivado has a built in simulator which will be ok for VHDL/Verilog simulation only - it is fairly capable.
If you want UVM or systemverilog, you will need modelsim or Cadence Simulator.
Cadence is really terrible when it comes to cross language support (making VHDL talk to SV is really really bad - they insist on only std_logic/std_logic_vector only, and absolutly no nested records!). The only bug Ive seen for this in Questa is when VHDL has a 0 length array, but thats mostly a langauge rather than tool issue.