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formality failing points
Hi All,
1. RTL vs Netlist comparation with Formality. I read SVF file successfully, but some svf operations rejected. Is verification OK for formality ?
2. There are some failing point when i do verification with formality. I analyze one of the failing point, and...
Dear all, do you meet the situation that silicon is different from pattern simulator in scan pattern simulation?
Silicon has some problems in shift pattern
It seems the chain has 2443 scan cells in ATE rather than 2444 in simulatior NC in shift pattern. The silicon seems to lose one cycle...
Re: ATPG pattern valid ?
Guys, thanks for your reply.
I have checked the result of PT and hold time has been cleaned.
but capture process still fail. God, almost drives me crazy.
Added after 2 minutes:
I change scan clock from 10MHz to 1MHz
But the capture problems are still there
Re: ATPG pattern valid ?
When I test my generated pattern after ATPG
There r some errors during measure PO and capture process with NC
what can I do with errors?
Are patterns wrong?
How can I debug the problems?
Added after 35 minutes:
My pattern is serial pattern.
But measure PO dont...
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