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ATPG pattern valid ? - errors during measure PO

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toobad365

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Re: ATPG pattern valid ?

When I test my generated pattern after ATPG
There r some errors during measure PO and capture process with NC
what can I do with errors?
Are patterns wrong?
How can I debug the problems?

Added after 35 minutes:

My pattern is serial pattern.
But measure PO dont pass, What should I do?
If shift pattern or capture pattern dont pass? What can I do?

Added after 36 minutes:

I simulated the pattern with the sdf file from PT
There are some errors?
What can I do?
 

ATPG pattern valid ?

i guess the timing closed in PT less than period in pattern. try running at slower frequency
 

ATPG pattern valid ?

hello friend,

Just check if your library model supports negative timing checks or not. Mostlikely, it is common issue at this stage.

Also u can check whether hold timing is clean in PT or not.

asic-dft.com
 

Re: ATPG pattern valid ?

Guys, thanks for your reply.
I have checked the result of PT and hold time has been cleaned.
but capture process still fail. God, almost drives me crazy.

Added after 2 minutes:

I change scan clock from 10MHz to 1MHz
But the capture problems are still there
 

ATPG pattern valid ?

U haven't confirmed if your library model supports negative timing checks or not.

1. In the sdf file (generated by PT), do u see any negative timing as shown below.
(HOLD (...edge SE) (..edge CLOCK) (-0.270:-0.123:-0.123))

If so, ur timing model has to support this kind of -ve timing checks.

Sunil Budumuru
asic-dft.com
 

Re: ATPG pattern valid ?

Please have a look at the warnings during DRC check stage.

toobad365 said:
When I test my generated pattern after ATPG
There r some errors during measure PO and capture process with NC
what can I do with errors?
Are patterns wrong?
How can I debug the problems?

Added after 35 minutes:

My pattern is serial pattern.
But measure PO dont pass, What should I do?
If shift pattern or capture pattern dont pass? What can I do?

Added after 36 minutes:

I simulated the pattern with the sdf file from PT
There are some errors?
What can I do?
 

Re: ATPG pattern valid ?

Warnings in ATPG log.

There might be some warnings during ATPG check. Some kind of circuit can cause mismatch between the values expected by ATPG and simulated by logic simulator.

sunilbudumuru said:
where r the warnings
 

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