Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
To be clear:
1. I have PHY layer chip which provide MII interface signals.
2. It is possible to get UDP/IP stack from opencores.org (https://opencores.org/project,udp_ip_stack) - it uses AXI interface to lower layer.
3. To connect 1. and 2. I could take
a) Xilinx Tri-Mode Ethernet Media...
Hi,
I want to implement UDP communication on my FPGA board. There is PHY layer, chip wit MII interface. Common approach in UDP/IP stacks for FPGA is AXI4 interface to lower layers. Even Xilinx has IPcores for MII to AXI4 interfacing.
In MII are signals:
RXD[3..0] - data
RXDV - RX_Data...
Hi,
this is very beginner question, but I can't find answer. I'm trying to create my first PCB. I have to create my own PCB component. It is in 16-pins Small Outline Package. Here are dimensions in millimeters from datasheet: .
I use component wizard and I'm not sure what size of pads I should...
Hello,
I have question about timing of SD card.
Do you know what is the maximum time in writing process between CMD sending and data. In specification is diagram: where P means one-cycle pull-up and * means repetition. So I understand it that after write command card waits for data start bit...
Yes, I know. But I want to learn BGA soldering. This is why I have prepared quite simple test board with not expensive BGA chip. The board is reviewed by my colleague. I could check after soldering all the IO ports. I know that I can destroy it but don't see other way to learn it, finally have...
Hello,
I'm preparing for my first BGA soldering and have to plan shopping list. My aim are FPGA chips. I have Jovy IR station and chips with balls. I know there is many descriptions in web, I read some threads, but not all is obvious for me so I want to ask directly. So what else I need...
Sorry but I don't understand it. Where to do that?
Having in component port like this (and tristate buffer code inside the component):
data_inout_comp: inout std_logic;
In top level I need to create port to assign pin to that port. So:
data_inout_top: inout std_logic;
And then must be that...
Hi,
I have component which should be connected to outside world and it has some ports to do it. Is it necessary to have that ports in component declaration in top module?
I know that I can create respective ports in top module, make connection in port map and assign them to pins in *.ucf file...
Thanks for help.
I tried PERIOD constraint, but there was no improvement. But after all project works even if ISE shows lower frequency :)
Now we can laugh at Planahead but it figures that I have to use it because it allows to work with bigger FPGA than Webpack version of ISE.
Hi,
in my design I use DCM on Spartan 3. When I set 25 MHz, ISE shows that possible max frequency for my design is over 170 MHz. Increasing DCM output to 50 MHz decreases max to about 90 MHz. If I set DCM output to 80 MHz, max is 55 MHz.
Input clock into DCM is 50 MHz from external oscillator...
Ehhh, I just didn't know that I need to click in Implementation=> Implement Design=> Translate/Map/P&R => Generate Synthesis Files. I thought it is generated automatically.
My design of course synthesize :D
Good to know/learn about association options for the future work. Thanks.
Hi,
I can do only Behavioral simulation. When I change simulation type to any other, UUT becomes empty and I can't add there my project.vhd file. Why it can happen? Is it because I use variables in my project?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
