timsanr
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Hi,
I want to implement UDP communication on my FPGA board. There is PHY layer, chip wit MII interface. Common approach in UDP/IP stacks for FPGA is AXI4 interface to lower layers. Even Xilinx has IPcores for MII to AXI4 interfacing.
In MII are signals:
RXD[3..0] - data
RXDV - RX_Data Valid,
COL - Collision Detect,
CRS - Carrier Sense,
RXER - Receive Error,
RXCLK - Receive clock.
But in AXI4 is a signal which indicates about last byte of the received frame, asserted in parallel with that last data byte.
I can't figure out how to generate such a signal when I have only RXDV which is deasserted when data is finished, one clock step too late.
I could check the type of packet and e.g. from UDP packets get the 'length' parameter, but e.g. ARP packets don't have 'length' parameter. Additionally real packet recognition is created in higher layers, it should be only interface.
Anyone knows the subject and can help with this?
EDIT:
Or maybe someone understands Verilog and can read this code, because I see that 'Rx_m ac_eop' signal is what I need:
https://opencores.org/project,ethernet_tri_mode
I want to implement UDP communication on my FPGA board. There is PHY layer, chip wit MII interface. Common approach in UDP/IP stacks for FPGA is AXI4 interface to lower layers. Even Xilinx has IPcores for MII to AXI4 interfacing.
In MII are signals:
RXD[3..0] - data
RXDV - RX_Data Valid,
COL - Collision Detect,
CRS - Carrier Sense,
RXER - Receive Error,
RXCLK - Receive clock.
But in AXI4 is a signal which indicates about last byte of the received frame, asserted in parallel with that last data byte.
I can't figure out how to generate such a signal when I have only RXDV which is deasserted when data is finished, one clock step too late.
I could check the type of packet and e.g. from UDP packets get the 'length' parameter, but e.g. ARP packets don't have 'length' parameter. Additionally real packet recognition is created in higher layers, it should be only interface.
Anyone knows the subject and can help with this?
EDIT:
Or maybe someone understands Verilog and can read this code, because I see that 'Rx_m ac_eop' signal is what I need:
https://opencores.org/project,ethernet_tri_mode
Last edited: