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Recent content by tiger_shark

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    Papoulis text book Edition 4 needed

    Hi there, Anyone has 4th edition of Probability book by Papoulis? Thank you
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    Pseudo Random noise Generator in VHDL

    vhdl noise generator Hi there, What distribution would you like your noise to have? are you using it as a channel noise emulator to simulate your communication list as additive Gaussian noise? In that case, simple LFSR would not work for you. In order to generate Gaussian pn noise (white)...
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    How to learn mobile communications with FPGA?

    Re: fpga - mobile comm Hi there, Would you like to learn these topics as manager(high level) or as engineer(implementation details, low level)? There are many FPGA / HDL books on this site. Also many digi-comm / DSP books available. It is a very broad area and depends on your background and...
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    Suggest me a simple project idea for BF533

    Hello, I have a EZ-KIT 533 board as well as Visual DSP 4.0 software. I would like to learn how do embedded programming, and explore BF533 capabilities, but even after digging into adi website, viewing the demos and ... , I really don't konw where to start, and waht to do with the setup. Maybe...
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    Verification using E language

    Hello all, Could anyone please help me with regard to which software I can use to do E programming for Verilog design verification? I konw that Spaceman Elite is the one but it does not seem to have a demo / free version or ... . Is any free tool availabe? I am reading the book "Design...
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    Mentor Graphics PADS PCB tool

    mentor graphics pads pcb Hello all, I am FPGA designer and I would like to learn how to work with a PCB / Layout tool. I need an example / tutorial to show me how to start from schematic and end up with a routed pcb. Does anyone know if I can find any kind of such tutorial? It can be very...
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    enquiry regarding start=up / opportunity in canada

    Hi, Does anyone know any start-up or small company doing FPGA/IP/Embedded /signal processing design? I am working in a bigger size company in Canada but I want to get exposed to more technical stuff rather than only FPGA / verilog. Any suggestions? Thanks, TS
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    Urgent verilog question, please help.

    Hi, THanks for the advise. How if the input to the module My_MODULE is itself a vector a[N-1], b[M-1]? Then how would you define a, b? Thanks TS Added after 25 minutes: yet another question: If the submodule MY_MODULE has a parameter, how can I use defparam to assign a value to all the...
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    Urgent verilog question, please help.

    Hi! In VHDL, you could use GENERIC and use for loop to instantiate variable number of modules, if need be. The synthesizer would then unfold the for loop and basically replicate the code as required. My question is : Do we have the same approach for verilog? For instance, I have a submodule...
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    Looking for a BF533 project mentor

    BF533 proposal Dear friends, I just got the BF533 EZ-Kit-Lite and the FPGA (s3)extender card + VDSP++ software at home for my hobby. I am in the need of a project (not very huge one) to start with and get guidance from an expert if needed. If anyone has a project which is targetting BF533...
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    Is decimation filter after or befor down sampling?

    In multi-rate systems, you first filter your signal to make sure the decimation does not affect any distotion to the data and then decimate. However, I have a feeling that your case is in different domain, something like a sigma/delta or st. TS
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    Group delay compensation in linear filter

    group delay compensation allpass filter As you know, FIR filters have inherently linear phase so no compensation is needed. For IIR, if you have the filter in MATLAB, you can use iirgrpdelay function in MATLAB and generate an all-pass filter with a desired groupdelay. Now, if your desired...
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    Question about Xilinx vs Lattice

    Hi, Thanks a lot for your reply to my inquiry. I found working with Lattice toolchain quite easy. Maybe I can ask one more general question from you: Is ther anything that Xilinx can do and Lattice Can't? or vise-versa? This woiuld be great help for me... I thank you again. Regards -TS
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    QUESTION ABOUT DCM and DLL frequence limitation

    Hey, I have been dealing wit SPartan3 DCMs (if interests you) and all these information can be found in its SPARTAN3 PLATFORM FPGA HANDBOOK which you can download for freee from www.xilinx.com Regards -TS
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    Question about Xilinx vs Lattice

    xilix vs lattice Hello , Would you please share your experience regarding Lattice in general and EPC2-50 specifically and compare it with Xilinx (s3-4000)? The project needs to be run at 160 - 200 MHz, need various IO standards, and needs to use parallel SRAM. I am interested to know if there...
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