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Recent content by Thawra-Kadeed

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    Re: Problems with DesignCompiler/PrimeTime Flow

    Re: Problems with DesignCompiler/PrimeTime Flow Thanks for interesting, actually I tried all that you mentioned and other attempts before I launch the issue but it didn't work. I think it's related more or less to the freq. itself which is going to go lower when we are using the gate level...
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    Re: Problems with DesignCompiler/PrimeTime Flow

    Re: Problems with DesignCompiler/PrimeTime Flow Actualluy the error is in the verilog cell library file: # ** Error: /tools/synopsys_asic/cell_libs/UMC/65/verilog/uk65lscllmvbbh_sdf21.v(35589): $hold( posedge CK:2 ns, negedge D:2 ns, 1 ns ); # Time: 2 ns Iteration: 6 Instance...
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    Re: Problems with DesignCompiler/PrimeTime Flow

    Re: Problems with DesignCompiler/PrimeTime Flow Thanks all for your help. Now I am interested just in DC not in IC compiler and also in our institute we use Modeslim or Questasim. I followe for now this flow: 1- Using Design Compiler to generate netlist ==> A.vhd, A.sbpf 2- Using Modelsim to...
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    Re: Problems with DesignCompiler/PrimeTime Flow

    Re: Problems with DesignCompiler/PrimeTime Flow In Design Compiler I used UMC db libraries from UMC vendor as a link libraries. For Modelsim, you mean I should use the .v library ,which is also provided from UMC , to define the standard cells and not the .db libraries ?
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    clock network power - prime time px

    Dear ThisIsNotSam, thnks for your attention. I know that if we have no inputs that doesn't mean we have no clock tree. For that I tried to search turning off the clk tree since there is no need to keep the circuit works and consume power where we don't have inputs. But any way, I can simply...
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    Re: Problems with DesignCompiler/PrimeTime Flow

    Re: Problems with DesignCompiler/PrimeTime Flow Thanks ThisIsNotSam and slutarius for help. Dear slutarius, I didn't mention I need line be line instructions, just I wanted to make sure from the general steps. Any way I started with your flow that you mentioned above. But actually I just need...
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    clock network power - prime time px

    Thanks for your participation. I am trying to inject 2 diff. traffic to my design to estimate the switching power. I had good results where the switching power increases every time I load more data. But the thing is I was surprised a bit that the internal power is a bit high and then I...
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    clock network power - prime time px

    I have a question please related to the internal power produced by clock network. I am trying to apply 0 traffic to my design to see how much switching power would consume, which should be so small. Here in this case I have this results: Power Group Power Power Power...
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    Re: Problems with DesignCompiler/PrimeTime Flow

    Re: Problems with DesignCompiler/PrimeTime Flow So my flow is the following: 1/ Making RTL simulation of my design by Modelsim and generating RTL SAIF file . 2/ synthesis the design using DC and getting netlist A 3/ reading the netlist A and RTL SAIF file by Prime Time to estimate the power...
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    Re: Problems with DesignCompiler/PrimeTime Flow

    Re: Problems with DesignCompiler/PrimeTime Flow Thanks so much for your participation. 1/ SAIF generation: is done using Modelsim where I should use the netlist from the output of DC. but what do you mean by "Back-Annotation simulation" because the SAIF file from Modelsim is called...
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    Re: Problems with DesignCompiler/PrimeTime Flow

    Re: Problems with DesignCompiler/PrimeTime Flow Thanks so much for your answer. I have a comment please, are you sure the names in the gate-level in Modelsim would be the same names in the gate-level in Design Compiler. Because you know the names are changed from rtl to gate and we do that in...
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    Re: Problems with DesignCompiler/PrimeTime Flow

    Re: Problems with DesignCompiler/PrimeTime Flow Yes sure, thanks so much for your answer. Just I want to clarify before that the problem with setting libraries is solved and I don't see now any black box. But the problem now I don't see the annotation for all nets, I see just very few net are...
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    Re: Problems with DesignCompiler/PrimeTime Flow

    Re: Problems with DesignCompiler/PrimeTime Flow Hello, I have the same problem. I was aware enough for the different link commands between DC (link_library) and PT (link_path) but I still have the same problem when I read_ddc file.ddc Unable to resolve reference to x1 in top-level Creating...
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    ASIC switching activity

    I put this space just to make the error clear for you, but no in reality there is no space. I was wondering whether using prime time in more helpful. But I also need DC to make the synthesis and this needs the ready saif file before. I hope any one here has an idea about that. Thanks
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    ASIC switching activity

    Thanks a lot for your reply. Unfortunately it's the same, but I tried Questasim rather than Modelsim and it worked and I saw the important data signal in the output like: (data_in\[0\] . data\[0\] (T0 6) (T1 1990) (TX 4) (TC 1) (IG 0)) But when I tried to read this saif file in the synopsys...
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