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Trying to follow the example in Allen's book for a two stage op-amp design (6.3)
Could someone explain the constraints placed on the common mode input range?
Vin_max = VDD - sqrt(I5/beta3) - |VT03max| + VT1min
Vin_min = VSS + sqrt(I5/beta1) + |VT1max| +VDS5(sat)
I don't understand his...
tsmc 0.18 model
spectre can handle the spice model files - i use TSMC18 MOSIS process and here is what I used (almost directly from their website)
these are plain text files (use emacs/vi/notepad), i just named them .doc as its the only allowed extension
goodluck
Hi,
I'm beginning VLSI student working on a 16-bit simplified datapath design. I have bitslice instances that I need to instantiate and array, but I do not wish to make control line connections for each part - I'd like to become proficient with the cadence tools.
From reading the manual and...
hspice ade
Hello,
I'm a student working through an introductory VLSI course at my university using the NCSU 1.6 beta PDK. The divaEXT.rul set uses NCSU_Analog_Parts kit included to extract my layout information for simulation and this kit does not have information for hspiceD. We use a...
how to record a good video lecture
I use firefox 3.0 with the "DownloadHelper" add-on:
https://addons.mozilla.org/en-US/firefox/addon/3006
Regards,
Brian
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