Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by techgig

  1. T

    cadence innovus help

    Hi, I'm new to innovus. From where I can get the help which are related to innovus tool. Please help me. Thanks.
  2. T

    Why d flip flops are most commonly used commercially?

    Thanks a lot ads-ee, that was the wonderful explanation!
  3. T

    Vdd and vss are exchanged

    Thanks Fvm and crutschow for better explaining!
  4. T

    Std cells layout design metal layer1 restriction

    Hi dick, can you please explain in simple way.
  5. T

    Vdd and vss are exchanged

    Hi, What happens when Vdd and vss are exchanged. Please explain me by taking the example of cmos inverter circuit. Thanks.
  6. T

    Std cells layout design metal layer1 restriction

    Hi, In std cells layout design why it is restricted to metal layer1 only? Please help me in this. Thanks.
  7. T

    Transistors with different threshold voltages

    Hi, why there are transistors with different threshold voltages are used in the circuit? Thanks.
  8. T

    Why d flip flops are most commonly used commercially?

    Hi, Why d flip flops are most commonly used commercially? Thanks.
  9. T

    [SOLVED] Different layers in vituoso

    Thanks a lot dick_freebird! That helped me in getting deep insight into it.
  10. T

    [SOLVED] Different layers in vituoso

    Hi all, I'm new to Cadence Virtuoso. Please help me with the different layers used and why they are used in virtuoso. In the below attached screenshot(it's for inverter, but not completed yet) I have got 2 doubts, namely 1. For both PMOS(top) & NMOS, why PIMP/NIMP is kept around poly? 2. For...
  11. T

    Capacitor at CMOS Inverter Output

    hi, please find the attached inverter image.
  12. T

    Capacitor at CMOS Inverter Output

    hi, why the capacitor is there at the output of the CMOS inverter? thanks in advance.
See more

Part and Inventory Search

Back
Top