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Std cells layout design metal layer1 restriction

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techgig

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Hi,

In std cells layout design why it is restricted to metal layer1 only?

Please help me in this.

Thanks.
 

erikl

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I think this stems from times of technologies with only 2 or 3 metal layers (≈2µm down to 0.35µm). To save space for inter-cell and over-cell routing.
 

dick_freebird

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No matter how many levels, you want to impose the
fewest routing barriers. Sometimes you will see poly
used as local interconnect (or crossunders), even,
although this is frowned upon generally. Even a small
bit of (say) metal2 in a few standard cells can have a
ripple effect making a lot of lines dodge it, and each
other, adding to both chip and routing-wall-time bloat.
 

techgig

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Hi dick, can you please explain in simple way.
 

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