Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have been studying about metastability and its details. It is said that synchronization chain registers are used to solve the problem of metastability. I want to know what is the importance of parameter 'Tmet' in calculation of MTBF and what is meant by 'timing slack' of registers in...
I am trying to implement a FSM but there are 3 different versions using which a FSM can be designed(It is mentioned in Xilinx XST guide).Each version uses different number of Process.
process1: process (clk,reset)
begin
if (reset ='1') then
state <=s1;
elsif (clk='1' and...
Yes, after i removed the initialization and explicitly assigned all the signals in each and every branch of if-else conditions the error was removed.
But I have used this methodology of initialization in a 3 process syntax of defining FSM as provided in XST guide. I think in single process style...
Thankyou, for pointing towards not including the default case in my code.But i would like to bring into light something relevant to this.
Before this Process, i had designed this same FSM using the three process style mentioned in Xilinx XST guide where we use 3 different processes to define our...
Should I intialize with something other than 'X' such as '0' or '1' as per the requirement of my FSM.
And I couldn't understand what you meant by 'default clause'.I mean from forums i have learnt that one should always initialize the signals before using them in a FSM process. Is 'default...
--This is a single process design of the FSM
Process(clk,rst)
begin
--Initialization of signals
state_s<=idle;
Tag_we_s<='0';
Dataram_we_s<='0';
Tag_write_s<="XX";
Valid_write_s<='X';
Dirty_write_s<='X';
Dataram_input_sel_s<='X';
Mem_we_out<='0'...
No, you already answered my question on the 2nd post and it solved my problem.
I was just asking if there is any other alternative to this methodology.I also got the answer to that as provided by "ads-ee"
Thanks for the suggestion.Yes, I observed that rewriting the .coe file then regenerating the core leads to the new initialization vectors being used to simulate.
But i was wondering that is there any other method to update the initialization of rom. Every time i want to implement with new...
I have created a ROM using distribute memory generator of COREgen and during the creation initiated it with a .coe file. But now i want to change the initialization of the ROM by changing the .coe file but i am unable to do it.
I have tried changing the .coe file when asked after double clicking...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
