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Hi All ,
I have internal and external violations in my design . By Internal I mean Reg to reg paths, By external I mean " Input pin to reg " and " reg to output pin " .
How to I go about fixing them ?? Should I remove my internal and external setup violations first and then fix hold ...
Hi Guys ,
What is the difference between running synthesis WITH clock as dont_touch_network [ get_ports clk ] and running synthesis WITHOUT setting clock as dont_touch_network ??? From the timing reports show that clock in both the cases is ideal . PLZ help .
Thanks
Thanks Guys for the clarification , Also in case I have
library_PVT_1.db
library_PVT_2.db
library_PVT_3.db ... and so on . In other words I have a huge list of .db's each one of them specific to one PVT . In this case how do I add my library's ?? should I link all of them ? While mapping to...
Hi All ,
I am new to DC and looking for some help . At present I have a verified design which I have to synthesize . What clock frequency should be set for the design ??? In other words a general question would be can a design be synthesized at any frequency or is there any range of...
Hi All ,
I am currently using magma for a quick timing analysis ( Not for sign off ) . The problem I am facing is this.
1) When I do a " report timing summary $m -internal -late " it gives me 27 failing endpoints for default mode , but when I do a " report timing path $m -internal -late...
Hi All,
I am a new to user of magma and I need some help regarding scripting.
How do I get a list of cells in the violating path ( specifically data path ) ? So that I can replace them with a different down-model of any type ??
Is there any way of doing this ?
Thanks,
Syed
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