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Synthesis using Synopsis Design compiler

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syed_dawood

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Hi All ,

I am new to DC and looking for some help . At present I have a verified design which I have to synthesize . What clock frequency should be set for the design ??? In other words a general question would be can a design be synthesized at any frequency or is there any range of frequency which depends on the design itself .??


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chrisyl

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Its up to your design requirements and the library you are using.
 

jirika

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Yes there is the highest frequency based on SETUP time. And your frequency should be lower.
 

syed_dawood

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Yes there is the highest frequency based on SETUP time. And your frequency should be lower.

Thanks Guys for the clarification , Also in case I have

library_PVT_1.db
library_PVT_2.db
library_PVT_3.db ... and so on . In other words I have a huge list of .db's each one of them specific to one PVT . In this case how do I add my library's ?? should I link all of them ? While mapping to cells from which .db will it pick up cells ??


Thanks.
 

chrisyl

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Typically, use the slowest library in DC.
The best way is to ask the foundry for setup signoff corners.
 

mail4idle2

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Please get the sign off corners and do run synthesi at that corner.
 

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