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Very very thanks rfsystem, I have found the problem. The rules doesn't match the process specs, I extract with a older rule file with no error. rfsystem suggests me to check and compare the rule file , hence i found the problem! thank you, rfsystem!
Thank you, rfsystem!
Would you explain the questio further more? I should search what? "um" or "m"? I have review the rules file, the units of length is "U". There are no places in the rules file to explicit utilize units, but all are numbers. You mean these numbers may be wrong?
I use Calibre to do the LPE, huanderds of capacitors are extracted. Much of the capacitor have a vaule 0.1fF~1pF, but several capacitor get a value 100F~1000F, unbelieveable! I use tsmc 0.18um 1p6m process!
pranam.bhagavan
Would you explain it in detail?
I don't thnik it is due to the power and ground signal because both of the layout and source have VDD and VSS.
the layout is generated by Encounter and Drc free. When I do LVS, calibre told me that there are some ports in the layout are missing from source netlist. I found that calibre regarded some "wire" nets of source netlist as ports and the top module of the netlist(generated from layout) has more...
I use cadence soc encounter & icfb to create a layout of a circuit with TSMC 0.18um process, but I got 1000+ _M6T.E.1 DRC errors in calibre. The errors info were listed as follows:
_M6T.E.1
1000 1000 3 Feb 25 20:17:35 2008
_M6T.E.1 { @ Min extension of a M6 region beyond a VIA5...
I'm designing some very small digital circuits, <100 gates. Could ic5141 read the tsmc stand cell library to extract the cells and instantiate these cells in layout editor? If can't, is there a simple way to get the layout without employee Synopsys DC and Canence P&R Tools?
My design is wirote in VHDL, but SOC Encounter read a verilog gate netlist file.
After the synthesis, Synopsys DC can generate gate-level netlist in both vhdl and verilog format. But I want to do post-layout simulation with VHDL gate-level netlist, is it possible? Does the sdf file could be...
hspice warning dvt0
a circuit levle model of inverter:
//////////////////////////////////////////////////////////////////////////////////////////
Inverter Circuit
.param Supply=1.8 * Set value of Vdd
.lib '../lib/mm018.l' TT * Set 0.18um library
.opt scale=0.1u * Set lambda (here lambda=0.10)...
In an architecture, I declared some procedures. And in the testbench, i want to call those procedures, how can i to do it? It seems that we can't do this by use EntityName.ProcedureName, just like in Verilog!
header files
use any editor, create the following three files:
///test.h
#ifndef __TEST_H__
#define __TEST_H__
int proc(int arg1);
#end if
///test.c
#include <stdio.h>
#include "test.h"
int proc(int arg1){
printf("Hello world!\n");
return 1;
}
////youproject.c
#include "test.h"
void...
Do you have the only one BC45 compiler? Someone said that BC40 are not so stable, I think you can use BC502. As I know, BC502 is money free now. But how can you find the books or reference mannual? Why not use MS VS 60 or GCC?
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