In VHDL, How To Call a PROCEDURE Cross Architecture?

[swgchlry]

In an architecture, I declared some procedures. And in the testbench, i want to call those procedures, how can i to do it? It seems that we can't do this by use EntityName.ProcedureName, just like in Verilog!

 

[aji_vlsi]

In an architecture, I declared some procedures. And in the testbench, i want to call those procedures, how can i to do it? It seems that we can't do this by use EntityName.ProcedureName, just like in Verilog!

You can't do that as hierarchical access is not allowed in VHDL (unlike Verilog). Put your procedure in a package and then you can achieve this.

Ajeetha, CVC
www.noveldv.com

 

[darylz]

put the procudure in a package and "use" it in each file