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I have a design with 20 -dff(d flops), 19 xnor and 18 nand gate, 15 inverters before scan insertion. after scan insertion i have 20 -sff (scan flops), 19 xnor and 18 nand gate, 15 inverters. now i want to know what is the gate overhead before and after scan insertion. how to calculate the gate...
Thank you very much dftrtl. And do you know about OPCG which is used for similar purpose. if so can you let me know .. how OPCG works to generate two clocks... i know how clock shaper works. Want to know if OPCG/OCCG has similar functionality.
The logic of the xor function:
A B OUT
--- ----
0 0 0
0 1 1
1 0 1
1 1 0
---------
Here, if the paths A,B is compressed to one path as OUT. The xor gate waits for input A and also for input B and gives an equivalent output thus helping in compressing the path to a single equivalent path...
Hi
How do we generate 2 at-speed pulses during transition ATPG, if the tester does not support it? is it through OPCG, clock leaker/shaper and so on or s there any other way. Im not sure of the solution for this. can any one help me?
Thanks,
Swetha
Hi,
DFT shadow logic is recommended to increase the testability of logic around modules for which the ATPG tools cannot generate test patterns. Shadow logic adds the ability to
(i) Observe the data on the nets connected to the inputs of the untestable logic
(ii) Control the nets connected to...
Thanks maulin & dftrtl. So my understanding in the requirement of transitional ATPG is as follows and correct me if i am wrong ... or need to understand more on it.
Nanometer technologies contain newer types of defects that are delay sensitive and can no longer be detected with traditional...
HI
I want to know the difference between on-product clock generator, on-chip clock generator, clock shaper?
as i know all these are used to shape the clock to get only two pulses - one launch and another capture pulse for at-speed testing. I want to know specifically what could be the...
Hi,
can any one tell me the comparison between LOC and LOS Transition ATPG? which is advantageous and which one has got limitations. which one of two gives better coverage and why so?
Thank you,
swetha
Re: delta sigma modulation
hi
can you share your code with me .. please it will be help full for me.. please if u dont mind... i have designed the interfacing circuitry for accelerometers using matlab.. now i have a task to built it with synopsis..and i am beginner.. can u please help mee. by...
Re: delta sigma spice
hi can you please help me with the second order sigma delta modulators in hspice ... need to code it in hspice to simulate it in synopsis.. can u send me more schematics if u have please.... which u have tried or .. so.. please in need of it urgently..
thank you
hi
i am working on interfacing systems for accelerometer.. i coded in matlab . now i need to do it in hspice. need help on designing a second order sigma -delta modulator using HSPICE.. I HOPE SOME ONE CAN HELP ME WITH THE SAMPLE CODE PLEASE... REQUIRE URGENTLY..
PLEASE MAIL TO...
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