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Recent content by supersonic_528

  1. S

    DFT Compiler: internally generated scan_mode signal

    Hi, In our design, the scan_mode signal is internally generated from a register controlled by JTAG and is not an input port. How do I define it for insert_dft to work properly? I cannot use the normal set_dft_signal command here as that would also need the "-port" option even if I use...
  2. S

    ASIC design job vs FPGA design job

    Hi folks, I am an ASIC design engineer with over 6 years experience. My experience in ASIC design spans across microarchitecture, RTL coding, synthesis, timing closure and verification. Is it advisable for me if I change to a FPGA design job? I mean, what are the pros and cons? I do not have...
  3. S

    ECO for setup violations

    Thanks for your reply. Why will option #2 be more close to post ECO situation than option #1 ?
  4. S

    ECO for setup violations

    If I have setup violations in my netlist and fixing them in PrimeTime, what kind of ECO is recommended and why? (1) Upsizing the cells (2) changing cell type from HVT to SVT/LVT (or from SVT to LVT) I was going with #1 but then someone told me #2 is better since it has less side effect on...
  5. S

    entering commands to Verdi through typing

    Hi all, Is there a way to enter commands in Verdi through a command line option (by typing)? I have always entered commands to Verdi using mouse. But now I have a list of signals and I want Verdi to trace their source and output the results. I do not want to do this manually, but would rather...
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    mixing clocks in a scan chain

    So basically if there is a capture path between FF1 (using clk1) and FF2 (using clk2), for capture cycle we are just toggling clk1 and not clk2. This is to avoid any timing issue on the path FF1/Q to FF2/D, correct? But are we not verifying timing on the same path already for functional mode? So...
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    mixing clocks in a scan chain

    Thanks for your reply, but I do not understand some of your answers very clearly. What is the restriction? Do they have to be synchronous or same frequency? But what if there is a capture/functional path between two flops with different clocks in the same chain? If we are not toggling both...
  8. S

    mixing clocks in a scan chain

    Hi, I am a bit confused about how scan works in ASIC designs, especially when we mix clocks in the same chain. On searching this forum, I found the following answer from a post on similar topic: https://www.edaboard.com/threads/199460/ You can mix the clocks on the same chain. For shifting...
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    "Design for Test" e-book request

    Hi, I am looking for the book "Design for Test : For Digital IC's and Embedded Core Systems" by Alfred Crouch. If anybody has its pdf version, can you please upload it. Many thanks.
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