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Of course it's the read operation causes the change of RAM content!!!
When I synchronize the address signals connected to the chip using the clock that the RAM used. It's OK!
So I can be so sure.
I met a question during my sample test.
In my opinion, a RAM will change its content when you write the data into it.But I found that read option alone will sometimes change the content of the RAM. So could anybody tell me why this happens? Or is this related to the foundary 's RAM?
Thanks!
It's not strange. Maybe you shall investigate the chip and find out each supply's aim.I once met a chip having four supply,1.2v,1.8v,2.5v,3.3v. The 3.3v is for TTL interface,2.5v is for lvds,lvpecl interface,...
Of course it's OK to do post_sim.
In our company, only STA and Fv is passed,then we will do post_sim. And we will not spend too much in post_sim. But at present,post_sim is still a must process.
I was involved in ASIC design for four years. In our company, I completed two chips. I took part in system design, write RTL codes, FPGA verification, chip synthesis, pt and so on(The work of post layout is done by foundary).
But these days,I am at a loss. I dont know which direction is...
I used asynchronous reset in my design, and now found in the test that the chip doesn't work stable.
Because the chip is about 5 million gates,so I don't apply synchronous reset in my design.
But now in the system test,there's need that I have to reset the datastream connecting to another...
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