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hi,
If i have library.v file containing D flip flop and other digital elements without specify block for delay then is it possible to do timing simulation using sdf file. Is specify block is mandatory to use sdf file for timing simulation, without specify block it is not possible ??
Regards
Sunil
I am working on JTAG TAP controller in which TDO pin is a tri state . What is the advantage of Tri state TDO pin in TAP controller plz expalin I need badly
Hi,
What are the advantages of having PULL UP resistor over PULL DOWN resistor interface . As most of the protocols have Pull Up resistor . Like I2C JTAG etc .Is there any specific advantage ?/
Plz answer
It is that MUX which is present in each Boundary cell which connects or disconnects the Boundary cell register from the design logic or from primary input pins.
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The same MUX that in previous image is in this image (MUX with mode as select line )
hi
Can any body plz explain the TAP controller IR decoder output lines connections to the various MUXs in TAP controller.
In the below Diagram the MUX at the output port has a select line . From where that select line will come is it come from IR-Decoder . IF from IR decoder then how the...
Thank your reply.
I am designing I2c master for my design like this . I did most of the coding but I am not getting how to define the START and STOP condition :-(
SCL =high
SDA=High---to--Low
SCL=High
SDA=Low--to--High
how to code this in verilog ??
If you have refernce design plz send It...
I am stuck in designing I2C master using verilog . Can anybody plz guide me how to implement START and STOP condition in I2C master using verilog . How to create that start and stop condition using verilog I am not getting plz its very much urgent
I am doing project using XILINX ISE and MODELSIM tool ?? My guide asked me to do Gate Level Simulation. I am not getting how to do Gate level Simulation ?? :-( Can anybody plz help which all files has to be consider to do GLS ??
Hi can anybody plz tell what is difference between NVRAM and EEPROM ??
NVRAM is non volatile RAM then why cant we consider it as Programmable ROM why it is not classified in ROM ??
hi
I got a job offer in matlab domain . Can anybody explain Wat is the use of Matlab in embedded system and career in Matlab domain ? I am Fpga student having good knowledge abt Fpga design can I able to get into Fpga having experience in Matlab ? plz explain Urgently
I recently read abt registerd FSM outputs i.e Registered Moore outputs and Registered Mealy Outputs , Can anybody explain wat is FSM output registered ?
I did verilog coding for 1011 Sequence detector for both moore and Mealy machine and I got the output like in the Image there is one clock...
If we do 1bit logical left shift in a 8 bit register then the
new value=2 times the old value
suppose the Old value is 10000010 (130 in decimal)
then the New value 00000100 (4 in decimal)
then the statement left shift will produce 2 times the old value will not be true
can anybody plz explain...
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