Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by srijesh

  1. S

    Explanation of recovery time and clock reconvergence

    recovery and removal time Hi, Check this SDF doc. Search for removal/recovery.
  2. S

    Winspice stops at doing transient analysis

    Winspice problem attach your netlist.
  3. S

    How to confirm the W/L of a transistor in a circuit?

    I think you need to get your hands to a Circuit Design book. For starters, you decide this by keeping things like Current, process, and transconductance in mind..
  4. S

    MC simulations in Winspice

    HI, Could anyone clarify if Monte Carlo simulations are possible in Winspice?? And if yes, the procedure?? I have performed this in other simulators, But is this option available in free version of winspice??
  5. S

    Looking for a good book about wireload models

    wireloadmodels You could start with CMOS VLSI DESIGN by Weste & harris.
  6. S

    Whats the basis for deciding the width and height of a cell

    standard cell hight trurl, why would the place & route tool decide that??
  7. S

    Help me on opamp simulation

    Yep, that is true. You could possibly fine tune your Overdrive by appropriate sizing. About the slew rate, i see the loading is about 14pf. Is that what you would see in actual scenario??[/u]
  8. S

    How to check analog circuit signal intergity

    HyperLynx is used for Signal Integrity. PADS is mainly for Layout. However, i am a little confused about your subject "Analog" signal integrity. SI is generally concerned to the digital realm.
  9. S

    Help me on opamp simulation

    supercede, change your pulse source from (2 1 200ns) to (3 0 200ns)
  10. S

    Getting layout of a circuit from schematics

    Re: help on layout design SDL -Schematic driven layout option is available in a few tools. This could be used in a few digital layouts. Certainly not prefered in Analog Layouts. One major problem in this flow is that you need to flatten out the design if changes are required. If you do that ECO...
  11. S

    image frequency in fm recievers

    calculate fm image frequency Image would be at 2*IF away from RF

Part and Inventory Search

Back
Top