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Thank you but you don't have to apologize. I might misunderstood your sayings as well. :) I always want to experiment and select which seems to be the best for each situation. That's why I have asked for Hints.
Yes, I agree about the gated-clock. I have done asynchronous alot in the past and...
I have checked your code but I am still doing the code with x2 clock to check if it behaves accordingly. checking every possible implementation once a time :) This was just a small part off all the signals I have to implement under this status , so it is taking tame.I have not reject reading...
Since each state takes one clock cycle Even if I x2 the clock speed then the state will change in one clock cycle but faster. Sorry but I cannot understand what will be the difference. The waveform states that B & C change logic in half clock cycle not in a full clock cycle.
Tricky thank you very much . I cannot change the speed of the clock. But in any case even if I change the speed of the clock the signals B & C will change in a clock cycle (full) and not as the diagram shows (half cycle).
Hello,
I am rather new on VHDL. I have done some code in the past but I have a problem concerning how to manipulate B and C signals (as shown below). Actually, it is a state machine and I am trying to change the logic of these signals (B & C) in half of the clock pulse. Could you please give...
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