Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by spade7

  1. S

    [VHDL] How to change signal logic

    Thank you all very much! Everything runs really good with the insertion of the second clk! :) :) :)
  2. S

    [VHDL] How to change signal logic

    Thank you but you don't have to apologize. I might misunderstood your sayings as well. :) I always want to experiment and select which seems to be the best for each situation. That's why I have asked for Hints. Yes, I agree about the gated-clock. I have done asynchronous alot in the past and...
  3. S

    [VHDL] How to change signal logic

    I have checked your code but I am still doing the code with x2 clock to check if it behaves accordingly. checking every possible implementation once a time :) This was just a small part off all the signals I have to implement under this status , so it is taking tame.I have not reject reading...
  4. S

    [VHDL] How to change signal logic

    Thank you all very much for the help!:)
  5. S

    [VHDL] How to change signal logic

    Since each state takes one clock cycle Even if I x2 the clock speed then the state will change in one clock cycle but faster. Sorry but I cannot understand what will be the difference. The waveform states that B & C change logic in half clock cycle not in a full clock cycle.
  6. S

    [VHDL] How to change signal logic

    Tricky thank you very much . I cannot change the speed of the clock. But in any case even if I change the speed of the clock the signals B & C will change in a clock cycle (full) and not as the diagram shows (half cycle).
  7. S

    [VHDL] How to change signal logic

    Do you mean to have a second clock for the signals B & C which runs on double speed of the global clock? This is Implemented on FPGA . Am I correct?
  8. S

    [VHDL] How to change signal logic

    Hello, I am rather new on VHDL. I have done some code in the past but I have a problem concerning how to manipulate B and C signals (as shown below). Actually, it is a state machine and I am trying to change the logic of these signals (B & C) in half of the clock pulse. Could you please give...

Part and Inventory Search

Back
Top