Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi matter,
Thanks for your reply, the global useful skew should be considered too. And another question, what 's your method to fix a design which data path is almost reasonable and with no margin? Except for useful skew , what else?
Hello every one,
For one certain design, data path almost has no margin, so i have to fix setup violation by useful skew. So i check slack margin before/after violation path and set_clock_tree_exception on clock pin.
While the result is, some violation was fixed by...
Hi dementu666,
Thanks for your replay, before i see your reply i've tried in this way, and tools run time is shorter than the method i meantioned above. I know i will miss the real violation by doing this. But i am sure these net will be routed by hand with special layer. So in this...
hello everybody,
There are some nets which cause lots of false violation. So i just want to ignore routing on these nets Or ignore DRC check on these nets. You know with these false violation the speed will be slow and slow. Do you know the setting?
I mean when you want to route a...
Yes, i am sure. normally, the manufacture grid should be 0.005. And 414 is integer , so the tools do not need to modify it to 414.134. This is why i am confusing.
Hi rca,
1. the instant can be place well manually
2. the point is that the location in DEF file is 414, while after defIn, the location was changed by tools, i find it is 414.134. Why it is ? How i can force encounter to do this defIn operation by 414??
Hi guys,
i generate a file named kaka.def,and part of the words like this:
-----------------------
- instA PAVDD_18 + SOURCE + DIST +FIXED ( 414000 0 ) N ;
---------------------------------
and i do defIn in encounter, in the GUI, i find that instA's location is not 414 yet, while...
I think "ESD implanted NMOS IO buffers" include "NMOS in IO protection circuits"
I will do like this.
By the way, does the scribe line guard ring should use PAD layer? Why?
thanks
Oh, my god.
In this case, I have to promise that i 've understood all the rules correctly. The words in green font is from design-rule. This rule does not mention NMOS used as IO protect circuit. Then, does it mean that i should use SAB to cover all the region of an NMOS In IO protect...
thanks, i'v got it.
but, the layout drawn as (A) can't be extracted out any mos FET just because of SAB. then, What i should do to extracted mos FET out?
ESD protect circuit layout
Which one is right?
(A) is mentioned in design-rule. SAB covers poly region
(B) comes from certain practice ESD protect circuit layout. SAB covers Drain region.
Which one do you think is right?
thanks a lot.
**broken link removed**
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
